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[Qemu-devel] [PULL 03/10] softfloat: For Mips only, correct default NaN
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 03/10] softfloat: For Mips only, correct default NaN values |
Date: |
Sun, 26 Jun 2016 14:38:35 +0100 |
From: Aleksandar Markovic <address@hidden>
Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct default NaN values (in their 16-, 32-, and 64-bit flavors).
For more info, see [1], page 84, Table 6.3 "Value Supplied When a New
Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN
Encodings".
[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
[2] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
fpu/softfloat-specialize.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 981d665..a1bcb46 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status)
if (status->snan_bit_is_one) {
return const_float16(0x7DFF);
} else {
+#if defined(TARGET_MIPS)
+ return const_float16(0x7E00);
+#else
return const_float16(0xFE00);
+#endif
}
#endif
}
@@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status)
if (status->snan_bit_is_one) {
return const_float32(0x7FBFFFFF);
} else {
+#if defined(TARGET_MIPS)
+ return const_float32(0x7FC00000);
+#else
return const_float32(0xFFC00000);
+#endif
}
#endif
}
@@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status)
if (status->snan_bit_is_one) {
return const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
} else {
+#if defined(TARGET_MIPS)
+ return const_float64(LIT64(0x7FF8000000000000));
+#else
return const_float64(LIT64(0xFFF8000000000000));
+#endif
}
#endif
}
--
2.7.4
- [Qemu-devel] [PULL 00/10] target-mips queue, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 02/10] softfloat: Clean code format in fpu/softfloat-specialize.h, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 03/10] softfloat: For Mips only, correct default NaN values,
Leon Alrae <=
- [Qemu-devel] [PULL 04/10] softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd(), Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 05/10] linux-user: Update preprocessor constants for Mips-specific e_flags bits, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 06/10] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 07/10] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 01/10] softfloat: Implement run-time-configurable meaning of signaling NaN bit, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 08/10] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 09/10] target-mips: Implement FCR31's R/W bitmask and related functionalities, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 10/10] target-mips: Add FCR31's FS bit definition, Leon Alrae, 2016/06/26
- Re: [Qemu-devel] [PULL 00/10] target-mips queue, Peter Maydell, 2016/06/27