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[Qemu-devel] [PULL 07/10] target-mips: Add abs2008 flavor of <ABS|NEG>.<
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 07/10] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D> |
Date: |
Sun, 26 Jun 2016 14:38:39 +0100 |
From: Aleksandar Markovic <address@hidden>
Updated handling of instructions <ABS|NEG>.<S|D>. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore,
any NaN operand causes signaling invalid operation), while abs2008
ones are non-arithmetic, always and only changing the sign bit, even
for NaN-like operands. Details on these instructions are documented
in [1] p. 35 and 359.
Implementation-wise, abs2008 versions are implemented without helpers,
for simplicity and performance sake.
[1] "MIPS Architecture For Programmers Volume II-A:
The MIPS64 Instruction Set Reference Manual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
Signed-off-by: Thomas Schwinge <address@hidden>
Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 26 ++++++++++++++++++++++----
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a1a9f75..661ca3a 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1435,6 +1435,7 @@ typedef struct DisasContext {
bool vp;
bool cmgcr;
bool mrp;
+ bool abs2008;
} DisasContext;
enum {
@@ -8890,7 +8891,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_abs_s(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
+ } else {
+ gen_helper_float_abs_s(fp0, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -8909,7 +8914,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- gen_helper_float_chs_s(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
+ } else {
+ gen_helper_float_chs_s(fp0, fp0);
+ }
gen_store_fpr32(ctx, fp0, fd);
tcg_temp_free_i32(fp0);
}
@@ -9380,7 +9389,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_abs_d(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
+ } else {
+ gen_helper_float_abs_d(fp0, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -9401,7 +9414,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- gen_helper_float_chs_d(fp0, fp0);
+ if (ctx->abs2008) {
+ tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
+ } else {
+ gen_helper_float_chs_d(fp0, fp0);
+ }
gen_store_fpr64(ctx, fp0, fd);
tcg_temp_free_i64(fp0);
}
@@ -19786,6 +19803,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct
TranslationBlock *tb)
(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
restore_cpu_state(env, &ctx);
#ifdef CONFIG_USER_ONLY
ctx.mem_idx = MIPS_HFLAG_UM;
--
2.7.4
- [Qemu-devel] [PULL 00/10] target-mips queue, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 02/10] softfloat: Clean code format in fpu/softfloat-specialize.h, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 03/10] softfloat: For Mips only, correct default NaN values, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 04/10] softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd(), Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 05/10] linux-user: Update preprocessor constants for Mips-specific e_flags bits, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 06/10] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 07/10] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>,
Leon Alrae <=
- [Qemu-devel] [PULL 01/10] softfloat: Implement run-time-configurable meaning of signaling NaN bit, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 08/10] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 09/10] target-mips: Implement FCR31's R/W bitmask and related functionalities, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 10/10] target-mips: Add FCR31's FS bit definition, Leon Alrae, 2016/06/26
- Re: [Qemu-devel] [PULL 00/10] target-mips queue, Peter Maydell, 2016/06/27