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[Qemu-devel] [PULL 03/23] ppc: Use a helper to filter writes to LPCR
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 03/23] ppc: Use a helper to filter writes to LPCR |
Date: |
Fri, 1 Jul 2016 16:41:39 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This handles filtering bits based on what is implemented by a
given architecture version. We also use it to copy to LPCR
some of the relevant 970 HID4 bits.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/mmu-hash64.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate_init.c | 56 +++++++++++++++++++++++++++++---------------
3 files changed, 95 insertions(+), 19 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5056ac2..c532b44 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -16,6 +16,7 @@ DEF_HELPER_1(rfmci, void, env)
DEF_HELPER_2(pminsn, void, env, i32)
DEF_HELPER_1(rfid, void, env)
DEF_HELPER_1(hrfid, void, env)
+DEF_HELPER_2(store_lpcr, void, env, tl)
#endif
DEF_HELPER_1(check_tlb_flush, void, env)
#endif
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 5b7b5e9..6d6f26c 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -851,3 +851,60 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
*/
tlb_flush(CPU(cpu), 1);
}
+
+void helper_store_lpcr(CPUPPCState *env, target_ulong val)
+{
+ uint64_t lpcr = 0;
+
+ /* Filter out bits */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_64B: /* 970 */
+ if (val & 0x40) {
+ lpcr |= LPCR_LPES0;
+ }
+ if (val & 0x8000000000000000ull) {
+ lpcr |= LPCR_LPES1;
+ }
+ if (val & 0x20) {
+ lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
+ }
+ if (val & 0x4000000000000000ull) {
+ lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
+ }
+ if (val & 0x2000000000000000ull) {
+ lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
+ }
+ env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
+
+ /* XXX We could also write LPID from HID4 here
+ * but since we don't tag any translation on it
+ * it doesn't actually matter
+ */
+ /* XXX For proper emulation of 970 we also need
+ * to dig HRMOR out of HID5
+ */
+ break;
+ case POWERPC_MMU_2_03: /* P5p */
+ lpcr = val & (LPCR_RMLS | LPCR_ILE |
+ LPCR_LPES0 | LPCR_LPES1 |
+ LPCR_RMI | LPCR_HDICE);
+ break;
+ case POWERPC_MMU_2_06: /* P7 */
+ lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
+ LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
+ LPCR_MER | LPCR_TC |
+ LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
+ break;
+ case POWERPC_MMU_2_07: /* P8 */
+ lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
+ LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
+ LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
+ LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
+ break;
+ default:
+ ;
+ }
+ env->spr[SPR_LPCR] = lpcr;
+}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d328455..af7a790 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7525,16 +7525,6 @@ static void gen_spr_970_hior(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_970_lpar(CPUPPCState *env)
-{
- /* Logical partitionning */
- /* PPC970: HID4 is effectively the LPCR */
- spr_register(env, SPR_970_HID4, "HID4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-}
-
static void gen_spr_book3s_common(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
@@ -7787,15 +7777,6 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
0x00000000);
}
-static void gen_spr_power5p_lpar(CPUPPCState *env)
-{
- /* Logical partitionning */
- spr_register_kvm(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
-}
-
#if !defined(CONFIG_USER_ONLY)
static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
{
@@ -7807,7 +7788,44 @@ static void spr_write_hmer(DisasContext *ctx, int sprn,
int gprn)
spr_store_dump_spr(sprn);
tcg_temp_free(hmer);
}
+
+static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
+}
+
+static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
+{
+#if defined(TARGET_PPC64)
+ spr_write_generic(ctx, sprn, gprn);
+ gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
+#endif
+}
+
+#endif /* !defined(CONFIG_USER_ONLY) */
+
+static void gen_spr_970_lpar(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* Logical partitionning */
+ /* PPC970: HID4 is effectively the LPCR */
+ spr_register(env, SPR_970_HID4, "HID4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_970_hid4,
+ 0x00000000);
+#endif
+}
+
+static void gen_spr_power5p_lpar(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* Logical partitionning */
+ spr_register_kvm(env, SPR_LPCR, "LPCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_lpcr,
+ KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
#endif
+}
static void gen_spr_book3s_ids(CPUPPCState *env)
{
--
2.7.4
- Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, (continued)
- Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, Mark Cave-Ayland, 2016/07/09
- Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, Cédric Le Goater, 2016/07/09
- Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, Benjamin Herrenschmidt, 2016/07/09
- Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, Cédric Le Goater, 2016/07/09
[Qemu-devel] [PULL 18/23] target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso, David Gibson, 2016/07/01
[Qemu-devel] [PULL 07/23] ppc: LPCR is a HV resource, David Gibson, 2016/07/01
[Qemu-devel] [PULL 09/23] hw/ppc/spapr: Add some missing hcall function set strings, David Gibson, 2016/07/01
[Qemu-devel] [PULL 22/23] spapr: drop duplicate variable in spapr_core_release(), David Gibson, 2016/07/01
[Qemu-devel] [PULL 11/23] spapr: Restore support for older PowerPC CPU cores, David Gibson, 2016/07/01
[Qemu-devel] [PULL 13/23] ppc: Fix 64K pages support in full emulation, David Gibson, 2016/07/01
[Qemu-devel] [PULL 03/23] ppc: Use a helper to filter writes to LPCR,
David Gibson <=
[Qemu-devel] [PULL 12/23] target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb, David Gibson, 2016/07/01
[Qemu-devel] [PULL 23/23] qmp: fix spapr example of query-hotpluggable-cpus, David Gibson, 2016/07/01
[Qemu-devel] [PULL 21/23] spapr: do proper error propagation in spapr_cpu_core_realize_child(), David Gibson, 2016/07/01
[Qemu-devel] [PULL 08/23] ppc: Print HSRR0/HSRR1 in "info registers", David Gibson, 2016/07/01
[Qemu-devel] [PULL 04/23] ppc: Fix conditions for delivering external interrupts to a guest, David Gibson, 2016/07/01
[Qemu-devel] [PULL 20/23] spapr: drop reference on child object during core realization, David Gibson, 2016/07/01
[Qemu-devel] [PULL 01/23] ppc: Add a bunch of hypervisor SPRs to Book3s, David Gibson, 2016/07/01
[Qemu-devel] [PULL 14/23] ppc/xics: Rename existing xics to xics_spapr, David Gibson, 2016/07/01
[Qemu-devel] [PULL 16/23] ppc/xics: Implement H_IPOLL using an accessor, David Gibson, 2016/07/01
[Qemu-devel] [PULL 19/23] spapr: Restore support for 970MP and POWER8NVL CPU cores, David Gibson, 2016/07/01