[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 1/4] ppc: simplify ppc_hash64_hpte_page_shift_no
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 1/4] ppc: simplify ppc_hash64_hpte_page_shift_noslb() |
Date: |
Mon, 4 Jul 2016 15:17:12 +1000 |
User-agent: |
Mutt/1.6.1 (2016-04-27) |
On Mon, Jul 04, 2016 at 02:46:51PM +1000, David Gibson wrote:
> On Fri, Jul 01, 2016 at 09:10:10AM +0200, Cédric Le Goater wrote:
> > The segment page shift parameter is never used. Let's remove it.
>
> I think I did have a use case for this in mind when I made it, but I
> can't remember what it was now. Oh well, we can always add it back
> when I remember. I'll apply this to ppc-for-2.7.
Actually.. no I won't. There are some problems in the later patches
in this series, and to fix this correctly we're going to need that
slb_pshift return value after all.
>
> >
> > Signed-off-by: Cédric Le Goater <address@hidden>
> > ---
> > hw/ppc/spapr_hcall.c | 4 ++--
> > target-ppc/mmu-hash64.c | 6 +-----
> > target-ppc/mmu-hash64.h | 3 +--
> > 3 files changed, 4 insertions(+), 9 deletions(-)
> >
> > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> > index e011ed4b664b..73af112e1d36 100644
> > --- a/hw/ppc/spapr_hcall.c
> > +++ b/hw/ppc/spapr_hcall.c
> > @@ -83,12 +83,12 @@ static target_ulong h_enter(PowerPCCPU *cpu,
> > sPAPRMachineState *spapr,
> > target_ulong pte_index = args[1];
> > target_ulong pteh = args[2];
> > target_ulong ptel = args[3];
> > - unsigned apshift, spshift;
> > + unsigned apshift;
> > target_ulong raddr;
> > target_ulong index;
> > uint64_t token;
> >
> > - apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel, &spshift);
> > + apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
> > if (!apshift) {
> > /* Bad page size encoding */
> > return H_PARAMETER;
> > diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> > index fa26ad2e875b..7d056c1e3b4a 100644
> > --- a/target-ppc/mmu-hash64.c
> > +++ b/target-ppc/mmu-hash64.c
> > @@ -610,14 +610,12 @@ static unsigned hpte_page_shift(const struct
> > ppc_one_seg_page_size *sps,
> > }
> >
> > unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> > - uint64_t pte0, uint64_t pte1,
> > - unsigned *seg_page_shift)
> > + uint64_t pte0, uint64_t pte1)
> > {
> > CPUPPCState *env = &cpu->env;
> > int i;
> >
> > if (!(pte0 & HPTE64_V_LARGE)) {
> > - *seg_page_shift = 12;
> > return 12;
> > }
> >
> > @@ -635,12 +633,10 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU
> > *cpu,
> >
> > shift = hpte_page_shift(sps, pte0, pte1);
> > if (shift) {
> > - *seg_page_shift = sps->page_shift;
> > return shift;
> > }
> > }
> >
> > - *seg_page_shift = 0;
> > return 0;
> > }
> >
> > diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
> > index 13ad060cfefb..f625de03da44 100644
> > --- a/target-ppc/mmu-hash64.h
> > +++ b/target-ppc/mmu-hash64.h
> > @@ -17,8 +17,7 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
> > target_ulong pte_index,
> > target_ulong pte0, target_ulong pte1);
> > unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> > - uint64_t pte0, uint64_t pte1,
> > - unsigned *seg_page_shift);
> > + uint64_t pte0, uint64_t pte1);
> > #endif
> >
> > /*
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
signature.asc
Description: PGP signature
- [Qemu-devel] [PATCH 0/4] ppc: fixes for large page and VRMA support, Cédric Le Goater, 2016/07/01
- [Qemu-devel] [PATCH 1/4] ppc: simplify ppc_hash64_hpte_page_shift_noslb(), Cédric Le Goater, 2016/07/01
- [Qemu-devel] [PATCH 2/4] ppc: fix large page support, Cédric Le Goater, 2016/07/01
- [Qemu-devel] [PATCH 3/4] ppc: simplify ppc_hash64_pteg_search(), Cédric Le Goater, 2016/07/01
- [Qemu-devel] [PATCH 4/4] ppc: fix VRMA support, Cédric Le Goater, 2016/07/01
- Re: [Qemu-devel] [PATCH 0/4] ppc: fixes for large page and VRMA support, Benjamin Herrenschmidt, 2016/07/04