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[Qemu-devel] [PATCH v11 17/28] intel_iommu: add support for split irqchi
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v11 17/28] intel_iommu: add support for split irqchip |
Date: |
Tue, 5 Jul 2016 16:19:18 +0800 |
In split irqchip mode, IOAPIC is working in user space, only update
kernel irq routes when entry changed. When IR is enabled, we directly
update the kernel with translated messages. It works just like a kernel
cache for the remapping entries.
Since KVM irqfd is using kernel gsi routes to deliver interrupts, as
long as we can support split irqchip, we will support irqfd as
well. Also, since kernel gsi routes will cache translated interrupts,
irqfd delivery will not suffer from any performance impact due to IR.
And, since we supported irqfd, vhost devices will be able to work
seamlessly with IR now. Logically this should contain both vhost-net and
vhost-user case.
Reviewed-by: Paolo Bonzini <address@hidden>
[move trace-events lines into target-i386/trace-events]
Signed-off-by: Peter Xu <address@hidden>
---
Makefile.objs | 1 +
hw/i386/intel_iommu.c | 7 +++++++
include/hw/i386/intel_iommu.h | 1 +
include/hw/i386/x86-iommu.h | 5 +++++
target-i386/kvm.c | 27 +++++++++++++++++++++++++++
target-i386/trace-events | 4 ++++
6 files changed, 45 insertions(+)
create mode 100644 target-i386/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index 7f1f0a3..6d5ddcf 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -153,6 +153,7 @@ trace-events-y += hw/alpha/trace-events
trace-events-y += ui/trace-events
trace-events-y += audio/trace-events
trace-events-y += net/trace-events
+trace-events-y += target-i386/trace-events
trace-events-y += target-sparc/trace-events
trace-events-y += target-s390x/trace-events
trace-events-y += target-ppc/trace-events
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 7cc6d18..71b274d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2167,6 +2167,12 @@ do_not_translate:
return 0;
}
+static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
+ MSIMessage *dst, uint16_t sid)
+{
+ return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), src, dst);
+}
+
static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
uint64_t *data, unsigned size,
MemTxAttrs attrs)
@@ -2412,6 +2418,7 @@ static void vtd_class_init(ObjectClass *klass, void *data)
dc->hotpluggable = false;
x86_class->realize = vtd_realize;
x86_class->find_add_as = vtd_find_add_as;
+ x86_class->int_remap = vtd_int_remap;
}
static const TypeInfo vtd_info = {
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index b3f17d7..3bca390 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -26,6 +26,7 @@
#include "hw/i386/x86-iommu.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/msi.h"
+#include "hw/sysbus.h"
#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
#define INTEL_IOMMU_DEVICE(obj) \
diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h
index 10779c1..b419ae5 100644
--- a/include/hw/i386/x86-iommu.h
+++ b/include/hw/i386/x86-iommu.h
@@ -22,6 +22,7 @@
#include "hw/sysbus.h"
#include "exec/memory.h"
+#include "hw/pci/pci.h"
#define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
#define X86_IOMMU_DEVICE(obj) \
@@ -32,6 +33,7 @@
OBJECT_GET_CLASS(X86IOMMUClass, obj, TYPE_X86_IOMMU_DEVICE)
#define X86_IOMMU_PCI_DEVFN_MAX 256
+#define X86_IOMMU_SID_INVALID (0xffff)
typedef struct X86IOMMUState X86IOMMUState;
typedef struct X86IOMMUClass X86IOMMUClass;
@@ -42,6 +44,9 @@ struct X86IOMMUClass {
DeviceRealize realize;
/* Find/Add IOMMU address space for specific PCI device */
AddressSpace *(*find_add_as)(X86IOMMUState *s, PCIBus *bus, int devfn);
+ /* MSI-based interrupt remapping */
+ int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
+ MSIMessage *dst, uint16_t sid);
};
struct X86IOMMUState {
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index f3698f1..bfa40b2 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -35,6 +35,7 @@
#include "hw/i386/apic.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic-msidef.h"
+#include "hw/i386/intel_iommu.h"
#include "exec/ioport.h"
#include "standard-headers/asm-x86/hyperv.h"
@@ -42,6 +43,7 @@
#include "hw/pci/msi.h"
#include "migration/migration.h"
#include "exec/memattrs.h"
+#include "trace.h"
//#define DEBUG_KVM
@@ -3323,6 +3325,31 @@ int kvm_device_msix_deassign(KVMState *s, uint32_t
dev_id)
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
uint64_t address, uint32_t data, PCIDevice *dev)
{
+ X86IOMMUState *iommu = x86_iommu_get_default();
+
+ if (iommu) {
+ int ret;
+ MSIMessage src, dst;
+ X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
+
+ src.address = route->u.msi.address_hi;
+ src.address <<= VTD_MSI_ADDR_HI_SHIFT;
+ src.address |= route->u.msi.address_lo;
+ src.data = route->u.msi.data;
+
+ ret = class->int_remap(iommu, &src, &dst, dev ? \
+ pci_requester_id(dev) : \
+ X86_IOMMU_SID_INVALID);
+ if (ret) {
+ trace_kvm_x86_fixup_msi_error(route->gsi);
+ return 1;
+ }
+
+ route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
+ route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
+ route->u.msi.data = dst.data;
+ }
+
return 0;
}
diff --git a/target-i386/trace-events b/target-i386/trace-events
new file mode 100644
index 0000000..2113075
--- /dev/null
+++ b/target-i386/trace-events
@@ -0,0 +1,4 @@
+# See docs/trace-events.txt for syntax documentation.
+
+# target-i386/kvm.c
+kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI
%" PRIu32
--
2.4.11
- [Qemu-devel] [PATCH v11 09/28] acpi: add DMAR scope definition for root IOAPIC, (continued)
- [Qemu-devel] [PATCH v11 09/28] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 10/28] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 11/28] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 12/28] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 13/28] intel_iommu: add IR translation faults defines, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 14/28] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 15/28] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 16/28] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 17/28] intel_iommu: add support for split irqchip,
Peter Xu <=
- [Qemu-devel] [PATCH v11 18/28] x86-iommu: introduce IEC notifiers, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 19/28] ioapic: register IOMMU IEC notifier for ioapic, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 20/28] intel_iommu: Add support for Extended Interrupt Mode, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 21/28] intel_iommu: add SID validation for IR, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 22/28] kvm-irqchip: simplify kvm_irqchip_add_msi_route, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 23/28] kvm-irqchip: i386: add hook for add/remove virq, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 24/28] kvm-irqchip: x86: add msi route notify fn, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 25/28] kvm-irqchip: do explicit commit when update irq, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 26/28] intel_iommu: support all masks in interrupt entry cache invalidation, Peter Xu, 2016/07/05
- [Qemu-devel] [PATCH v11 27/28] kvm-all: add trace events for kvm irqchip ops, Peter Xu, 2016/07/05