[Qemu-devel] [PULL 10/11] target-mips: support CP0.Config4.AE bit

[Leon Alrae]

From: Paul Burton <address@hidden>

The read-only Config4.AE bit set denotes extended 10 bits ASID.

Signed-off-by: Paul Burton <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
 target-mips/cpu.h       | 1 +
 target-mips/translate.c | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3e233ad..2c45839 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -468,6 +468,7 @@ struct CPUMIPSState {
     int32_t CP0_Config4_rw_bitmask;
 #define CP0C4_M    31
 #define CP0C4_IE   29
+#define CP0C4_AE   28
 #define CP0C4_KScrExist 16
 #define CP0C4_MMUExtDef 14
 #define CP0C4_FTLBPageSize 8
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 01510b3..bab52cb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20302,7 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
         env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
     }
-    env->CP0_EntryHi_ASID_mask = 0xff;
+    env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ?
+                                 0x3ff : 0xff;
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
     /* vectored interrupts not implemented, timer on int 7,
        no performance counters. */
-- 
2.7.4