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[Qemu-devel] [PULL 04/11] gic: provide defines for v2/v3 targetlist size
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/11] gic: provide defines for v2/v3 targetlist sizes |
Date: |
Thu, 14 Jul 2016 17:29:36 +0100 |
From: Andrew Jones <address@hidden>
Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/intc/arm_gic.h | 3 +++
include/hw/intc/arm_gicv3_common.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index 0971e37..42bb535 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -23,6 +23,9 @@
#include "arm_gic_common.h"
+/* Number of SGI target-list bits */
+#define GIC_TARGETLIST_BITS 8
+
#define TYPE_ARM_GIC "arm_gic"
#define ARM_GIC(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index f72e499..341a311 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -35,6 +35,9 @@
#define GICV3_MAXIRQ 1020
#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
+/* Number of SGI target-list bits */
+#define GICV3_TARGETLIST_BITS 16
+
/* Minimum BPR for Secure, or when security not enabled */
#define GIC_MIN_BPR 0
/* Minimum BPR for Nonsecure when security is enabled */
--
1.9.1
- [Qemu-devel] [PULL 00/11] target-arm queue, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 10/11] ast2400: pretend DMAs are done for U-boot, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 11/11] ast2400: externalize revision numbers, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 09/11] ast2400: replace aspeed_smc_is_implemented(), Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 08/11] hw/misc: fix typo in Aspeed SCU hw-strap2 property name, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 04/11] gic: provide defines for v2/v3 targetlist sizes,
Peter Maydell <=
- [Qemu-devel] [PULL 07/11] m25p80: Fix QIOR/DIOR handling for Winbond, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 05/11] hw/arm/virt: tcg: adjust MPIDR like KVM, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 06/11] target-arm: Add missed AArch32 TLBI sytem registers, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 03/11] target-arm: Use Neon for zero checking, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 02/11] Revert "hw/ptimer: Perform counter wrap around if timer already expired", Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 01/11] virtio-mmio: format transport base address in BusClass.get_dev_path, Peter Maydell, 2016/07/14
- Re: [Qemu-devel] [PULL 00/11] target-arm queue, Peter Maydell, 2016/07/14