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[Qemu-devel] [PULL 04/28] target-i386: Fill high bits of mtrr mask
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 04/28] target-i386: Fill high bits of mtrr mask |
Date: |
Wed, 20 Jul 2016 12:08:10 -0300 |
From: "Dr. David Alan Gilbert" <address@hidden>
Fill the bits between 51..number-of-physical-address-bits in the
MTRR_PHYSMASKn variable range mtrr masks so that they're consistent
in the migration stream irrespective of the physical address space
of the source VM in a migration.
Signed-off-by: Dr. David Alan Gilbert <address@hidden>
Suggested-by: Paolo Bonzini <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
include/hw/i386/pc.h | 5 +++++
target-i386/cpu.c | 1 +
target-i386/cpu.h | 3 +++
target-i386/kvm.c | 28 +++++++++++++++++++++++++++-
4 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index e38c95a..47411cb 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -377,6 +377,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = "vmxnet3",\
.property = "romfile",\
.value = "",\
+ },\
+ {\
+ .driver = TYPE_X86_CPU,\
+ .property = "fill-mtrr-mask",\
+ .value = "off",\
},
#define PC_COMPAT_2_5 \
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 669180e..5ac7e97 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -3328,6 +3328,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
+ DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index b2ddcb8..b2ab8bf 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1198,6 +1198,9 @@ struct X86CPU {
/* Compatibility bits for old machine types: */
bool enable_cpuid_0xb;
+ /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
+ bool fill_mtrr_mask;
+
/* Number of physical address bits supported */
uint32_t phys_bits;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 2f1cc62..df28dd2 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1977,6 +1977,7 @@ static int kvm_get_msrs(X86CPU *cpu)
CPUX86State *env = &cpu->env;
struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
int ret, i;
+ uint64_t mtrr_top_bits;
kvm_msr_buf_reset(cpu);
@@ -2129,6 +2130,30 @@ static int kvm_get_msrs(X86CPU *cpu)
}
assert(ret == cpu->kvm_msr_buf->nmsrs);
+ /*
+ * MTRR masks: Each mask consists of 5 parts
+ * a 10..0: must be zero
+ * b 11 : valid bit
+ * c n-1.12: actual mask bits
+ * d 51..n: reserved must be zero
+ * e 63.52: reserved must be zero
+ *
+ * 'n' is the number of physical bits supported by the CPU and is
+ * apparently always <= 52. We know our 'n' but don't know what
+ * the destinations 'n' is; it might be smaller, in which case
+ * it masks (c) on loading. It might be larger, in which case
+ * we fill 'd' so that d..c is consistent irrespetive of the 'n'
+ * we're migrating to.
+ */
+
+ if (cpu->fill_mtrr_mask) {
+ QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
+ assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
+ mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
+ } else {
+ mtrr_top_bits = 0;
+ }
+
for (i = 0; i < ret; i++) {
uint32_t index = msrs[i].index;
switch (index) {
@@ -2327,7 +2352,8 @@ static int kvm_get_msrs(X86CPU *cpu)
break;
case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
if (index & 1) {
- env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
+ env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
+ mtrr_top_bits;
} else {
env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
}
--
2.5.5
- [Qemu-devel] [PULL v2 00/28] x86 queue, 2016-07-20, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 01/28] target-i386: Provide TCG_PHYS_ADDR_BITS, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 02/28] target-i386: Allow physical address bits to be set, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 03/28] target-i386: Mask mtrr mask based on CPU physical address limits, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 04/28] target-i386: Fill high bits of mtrr mask,
Eduardo Habkost <=
- [Qemu-devel] [PULL 05/28] target-i386: Use uint32_t for X86CPU.apic_id, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 06/28] pc: Add x86_topo_ids_from_apicid(), Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 07/28] target-i386: Set physical address bits based on host, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 08/28] pc: Extract CPU lookup into a separate function, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 09/28] pc: cpu: Consolidate apic-id validity checks in pc_cpu_pre_plug(), Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 10/28] target-i386: Replace custom apic-id setter/getter with static property, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 11/28] target-i386: Add socket/core/thread properties to X86CPU, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 12/28] target-i386: Add support for UMIP and RDPID CPUID bits, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 13/28] target-i386: cpu: Do not ignore error and fix apic parent, Eduardo Habkost, 2016/07/20
- [Qemu-devel] [PULL 14/28] target-i386: Fix apic object leak when CPU is deleted, Eduardo Habkost, 2016/07/20