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Re: [Qemu-devel] [RFC v1 03/13] target-ppc: adding addpcis instruction
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-devel] [RFC v1 03/13] target-ppc: adding addpcis instruction |
Date: |
Thu, 21 Jul 2016 13:23:33 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Nikunj A Dadhania <address@hidden> writes:
> ISA 3.0 instruction for adding immediate value with next instruction
> address and return the result in the target register.
>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> Reviewed-by: David Gibson <address@hidden>
> ---
> target-ppc/translate.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 92030b6..93c7c66 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -432,6 +432,20 @@ static inline uint32_t name(uint32_t opcode)
> \
> return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |
> \
> ((opcode >> (shift2)) & ((1 << (nb2)) - 1));
> \
> }
> +
> +#define EXTRACT_HELPER_DXFORM(name,
> \
> + d0_bits, shift_op_d0, shift_d0,
> \
> + d1_bits, shift_op_d1, shift_d1,
> \
> + d2_bits, shift_op_d2, shift_d2)
> \
> +static inline int16_t name(uint32_t opcode)
> \
> +{
> \
> + return
> \
> + (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0))
> | \
> + (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1))
> | \
> + (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) <<
> (shift_d2)); \
> +}
> +
> +
> /* Opcode part 1 */
> EXTRACT_HELPER(opc1, 26, 6);
> /* Opcode part 2 */
> @@ -501,6 +515,9 @@ EXTRACT_HELPER(FPL, 25, 1);
> EXTRACT_HELPER(FPFLM, 17, 8);
> EXTRACT_HELPER(FPW, 16, 1);
>
> +/* addpcis */
> +EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
> +
> /*** Jump target decoding
> ***/
> /* Immediate address */
> static inline target_ulong LI(uint32_t opcode)
> @@ -984,6 +1001,15 @@ static void gen_addis(DisasContext *ctx)
> }
> }
>
> +/* addpcis */
> +static void gen_addpcis(DisasContext *ctx)
> +{
> + target_long d = DX(ctx->opcode);
I found a bug here, d has to be shifted by 16. Will update the patch
accordingly.
> +
> + tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip);
> + tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], d);
> +}
> +
Regards
Nikunj
- [Qemu-devel] [RFC v1 00/13] POWER9 TCG enablements - part1, Nikunj A Dadhania, 2016/07/18
- [Qemu-devel] [RFC v1 01/13] target-ppc: Introduce Power9 family, Nikunj A Dadhania, 2016/07/18
- [Qemu-devel] [RFC v1 02/13] target-ppc: Introduce POWER ISA 3.0 flag, Nikunj A Dadhania, 2016/07/18
- [Qemu-devel] [RFC v1 03/13] target-ppc: adding addpcis instruction, Nikunj A Dadhania, 2016/07/18
- Re: [Qemu-devel] [RFC v1 03/13] target-ppc: adding addpcis instruction,
Nikunj A Dadhania <=
- [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/18
- Re: [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations, David Gibson, 2016/07/22
- Re: [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/22
- Re: [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations, David Gibson, 2016/07/22
- Re: [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/22
- Re: [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations, David Gibson, 2016/07/22
- Re: [Qemu-devel] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/22
[Qemu-devel] [RFC v1 07/13] target-ppc: add cnttzd[.] instruction, Nikunj A Dadhania, 2016/07/18