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[Qemu-devel] [PULL v5 15/57] intel_iommu: set IR bit for ECAP register
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v5 15/57] intel_iommu: set IR bit for ECAP register |
Date: |
Thu, 21 Jul 2016 20:52:09 +0300 |
From: Peter Xu <address@hidden>
Enable IR in IOMMU Extended Capability register.
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/intel_iommu_internal.h | 2 ++
hw/i386/intel_iommu.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index b648e69..5b98a11 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -176,6 +176,8 @@
/* (offset >> 4) << 8 */
#define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
#define VTD_ECAP_QI (1ULL << 1)
+/* Interrupt Remapping support */
+#define VTD_ECAP_IR (1ULL << 3)
/* CAP_REG */
/* (offset >> 4) << 24 */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 26e322a..9c7a084 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1956,6 +1956,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,
PCIBus *bus, int devfn)
*/
static void vtd_init(IntelIOMMUState *s)
{
+ X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
+
memset(s->csr, 0, DMAR_REG_SIZE);
memset(s->wmask, 0, DMAR_REG_SIZE);
memset(s->w1cmask, 0, DMAR_REG_SIZE);
@@ -1977,6 +1979,10 @@ static void vtd_init(IntelIOMMUState *s)
VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
+ if (x86_iommu->intr_supported) {
+ s->ecap |= VTD_ECAP_IR;
+ }
+
vtd_reset_context_cache(s);
vtd_reset_iotlb(s);
--
MST
- [Qemu-devel] [PULL v5 05/57] hw/apb: fix PCI bus initialization, (continued)
- [Qemu-devel] [PULL v5 05/57] hw/apb: fix PCI bus initialization, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 06/57] hw/grackle: fix PCI bus initialization, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 07/57] hw/prep: realize the PCI root bus as part of the prep init, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 08/57] hw/versatile: realize the PCI root bus as part of the versatile init, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 09/57] x86-iommu: introduce parent class, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 10/57] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 11/57] x86-iommu: provide x86_iommu_get_default, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 12/57] x86-iommu: introduce "intremap" property, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 13/57] acpi: enable INTR for DMAR report structure, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 14/57] intel_iommu: allow queued invalidation for IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 15/57] intel_iommu: set IR bit for ECAP register,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v5 16/57] acpi: add DMAR scope definition for root IOAPIC, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 17/57] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 18/57] intel_iommu: handle interrupt remap enable, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 19/57] intel_iommu: define several structs for IOMMU IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 21/57] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 22/57] intel_iommu: get rid of {0} initializers, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 23/57] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 24/57] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 25/57] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/21