[Qemu-devel] [PATCH v12 6/9] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions

[Michael Rolnik]

Signed-off-by: Michael Rolnik <address@hidden>
---
 target-avr/cpu.h       |  13 ++-
 target-avr/helper.c    | 284 ++++++++++++++++++++++++++++++++++++++++++++++---
 target-avr/helper.h    |   8 +-
 target-avr/translate.c |   9 ++
 4 files changed, 299 insertions(+), 15 deletions(-)

diff --git a/target-avr/cpu.h b/target-avr/cpu.h
index 4bb3d6d..f362c26 100644
--- a/target-avr/cpu.h
+++ b/target-avr/cpu.h
@@ -140,6 +140,7 @@ struct CPUAVRState {
     uint32_t        sp;     /*   16 bits                            */
 
     uint64_t        intsrc; /*  interrupt sources                   */
+    bool            fullacc;/*  CPU/MEM if true MEM only otherwise  */
 
     uint32_t        features;
 
@@ -182,12 +183,22 @@ int avr_cpu_handle_mmu_fault(CPUState *cpu, vaddr 
address, int rw,
 int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf,
                                 int len, bool is_write);
 
+enum {
+    TB_FLAGS_FULL_ACCESS = 1,
+};
 static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc,
                                 target_ulong *cs_base, uint32_t *pflags)
 {
+    uint32_t flags = 0;
+
     *pc = env->pc_w * 2;
     *cs_base = 0;
-    *pflags = 0;
+
+    if (env->fullacc) {
+        flags |= TB_FLAGS_FULL_ACCESS;
+    }
+
+    *pflags = flags;
 }
 
 static inline int cpu_interrupts_enabled(CPUAVRState *env1)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index 3e61193..d1f254d 100644
--- a/target-avr/helper.c
+++ b/target-avr/helper.c
@@ -28,6 +28,7 @@
 #include "exec/cpu_ldst.h"
 #include "qemu/host-utils.h"
 #include "exec/helper-proto.h"
+#include "exec/ioport.h"
 
 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
@@ -42,14 +43,14 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int 
interrupt_request)
             cs->exception_index = EXCP_RESET;
             cc->do_interrupt(cs);
 
-            cs->interrupt_request   &= ~CPU_INTERRUPT_RESET;
+            cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
 
             ret = true;
         }
     }
     if (interrupt_request & CPU_INTERRUPT_HARD) {
         if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
-            int     index = ctz32(env->intsrc);
+            int index = ctz32(env->intsrc);
             cs->exception_index = EXCP_INT(index);
             cc->do_interrupt(cs);
 
@@ -64,8 +65,8 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int 
interrupt_request)
 
 void avr_cpu_do_interrupt(CPUState *cs)
 {
-    AVRCPU         *cpu = AVR_CPU(cs);
-    CPUAVRState    *env = &cpu->env;
+    AVRCPU *cpu = AVR_CPU(cs);
+    CPUAVRState *env = &cpu->env;
 
     uint32_t ret = env->pc_w;
     int vector = 0;
@@ -79,14 +80,14 @@ void avr_cpu_do_interrupt(CPUState *cs)
     }
 
     if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
-        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
-        stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >>  8);
-        stb_phys(cs->as, env->sp--, (ret & 0xff0000) >> 16);
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >>  8);
+        cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
-        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
-        stb_phys(cs->as, env->sp--, (ret & 0x00ff00) >>  8);
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >>  8);
     } else {
-        stb_phys(cs->as, env->sp--, (ret & 0x0000ff));
+        cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
     }
 
     env->pc_w = base + vector * size;
@@ -124,15 +125,55 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, 
MMUAccessType access_type,
     vaddr &= TARGET_PAGE_MASK;
 
     if (mmu_idx == MMU_CODE_IDX) {
-        paddr = PHYS_BASE_CODE + vaddr;
+        paddr = PHYS_BASE_CODE + vaddr - VIRT_BASE_CODE;
         prot = PAGE_READ | PAGE_EXEC;
     } else {
-        paddr = PHYS_BASE_DATA + vaddr;
-        prot = PAGE_READ | PAGE_WRITE;
+#if VIRT_BASE_REGS == 0
+        if (vaddr < VIRT_BASE_REGS + AVR_REGS) {
+#else
+        if (VIRT_BASE_REGS <= vaddr && vaddr < VIRT_BASE_REGS + SIZE_REGS) {
+#endif
+            /*
+                this is a write into CPU registers, exit and rebuilt this TB
+                to use full write
+            */
+            AVRCPU *cpu = AVR_CPU(cs);
+            CPUAVRState *env = &cpu->env;
+            env->fullacc = 1;
+            cpu_loop_exit_restore(cs, retaddr);
+        } else {
+            /*
+                this is a write into memory. nothing special
+            */
+            paddr = PHYS_BASE_DATA + vaddr - VIRT_BASE_DATA;
+            prot = PAGE_READ | PAGE_WRITE;
+        }
     }
 
     tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, page_size);
 }
+void helper_sleep(CPUAVRState *env)
+{
+    CPUState *cs = CPU(avr_env_get_cpu(env));
+
+    cs->exception_index = EXCP_HLT;
+    cpu_loop_exit(cs);
+}
+void helper_unsupported(CPUAVRState *env)
+{
+    CPUState *cs = CPU(avr_env_get_cpu(env));
+
+    /*
+        I count not find what happens on the real platform, so
+        it's EXCP_DEBUG for meanwhile
+    */
+    cs->exception_index = EXCP_DEBUG;
+    if (qemu_loglevel_mask(LOG_UNIMP)) {
+        qemu_log("UNSUPPORTED\n");
+        cpu_dump_state(cs, qemu_logfile, fprintf, 0);
+    }
+    cpu_loop_exit(cs);
+}
 
 void helper_debug(CPUAVRState *env)
 {
@@ -142,3 +183,220 @@ void helper_debug(CPUAVRState *env)
     cpu_loop_exit(cs);
 }
 
+void helper_wdr(CPUAVRState *env)
+{
+    CPUState *cs = CPU(avr_env_get_cpu(env));
+
+    /*
+        WD is not implemented yet, placeholder
+    */
+    cs->exception_index = EXCP_DEBUG;
+    cpu_loop_exit(cs);
+}
+
+/*
+    This function implements IN instruction
+
+    It does the following
+    a.  if an IO register belongs to CPU, its value is read and returned
+    b.  otherwise io address is translated to mem address and physical memory
+        is read.
+    c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
+
+*/
+target_ulong helper_inb(CPUAVRState *env, uint32_t port)
+{
+    target_ulong    data    = 0;
+
+    switch (port) {
+        case    0x38: {
+            data = 0xff & (env->rampD >> 16);  /*  RAMPD   */
+            break;
+        }
+        case    0x39: {
+            data = 0xff & (env->rampX >> 16);  /*  RAMPX   */
+            break;
+        }
+        case    0x3a: {
+            data = 0xff & (env->rampY >> 16);  /*  RAMPY   */
+            break;
+        }
+        case    0x3b: {
+            data = 0xff & (env->rampZ >> 16);  /*  RAMPZ   */
+            break;
+        }
+        case    0x3c: {
+            data = 0xff & (env->eind  >> 16);  /*  EIND    */
+            break;
+        }
+        case    0x3d: {                         /*  SPL     */
+            data = env->sp & 0x00ff;
+            break;
+        }
+        case    0x3e: {                         /*  SPH     */
+            data = env->sp >> 8;
+            break;
+        }
+        case    0x3f: {                         /*  SREG    */
+            data = cpu_get_sreg(env);
+            break;
+        }
+        default: {
+            /*
+                CPU does not know how to read this register, pass it to the
+                device/board
+            */
+
+            cpu_physical_memory_read(PHYS_BASE_REGS + port
+                                              + AVR_CPU_IO_REGS_BASE, &data, 
1);
+        }
+    }
+
+    /*  make a copy */
+    if (port < AVR_CPU_IO_REGS) {
+        env->io[port] = data;
+    }
+
+    return  data;
+}
+
+/*
+    This function implements OUT instruction
+
+    It does the following
+    a.  if an IO register belongs to CPU, its value is written into the 
register
+    b.  otherwise io address is translated to mem address and physical memory
+        is written.
+    c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
+
+*/
+void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
+{
+    data    &= 0x000000ff;
+
+    switch (port) {
+        case    0x04: {
+            qemu_irq    irq;
+            CPUState   *cpu = CPU(avr_env_get_cpu(env));
+            irq = qdev_get_gpio_in(DEVICE(cpu), 3);
+            qemu_set_irq(irq, 1);
+            break;
+        }
+        case    0x38: {
+            if (avr_feature(env, AVR_FEATURE_RAMPD)) {
+                env->rampD = (data & 0xff) << 16;   /*  RAMPD   */
+            }
+            break;
+        }
+        case    0x39: {
+            if (avr_feature(env, AVR_FEATURE_RAMPX)) {
+                env->rampX = (data & 0xff) << 16;   /*  RAMPX   */
+            }
+            break;
+        }
+        case    0x3a: {
+            if (avr_feature(env, AVR_FEATURE_RAMPY)) {
+                env->rampY = (data & 0xff) << 16;   /*  RAMPY   */
+            }
+            break;
+        }
+        case    0x3b: {
+            if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
+                env->rampZ = (data & 0xff) << 16;   /*  RAMPZ   */
+            }
+            break;
+        }
+        case    0x3c: {
+            env->eind = (data & 0xff) << 16;        /*  EIDN    */
+            break;
+        }
+        case    0x3d: {                             /*  SPL */
+            env->sp = (env->sp & 0xff00) | (data);
+            break;
+        }
+        case    0x3e: {                             /*  SPH */
+            if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
+                env->sp = (env->sp & 0x00ff) | (data << 8);
+            }
+            break;
+        }
+        case    0x3f: {                             /*  SREG */
+            cpu_set_sreg(env, data);
+            break;
+        }
+        default: {
+            /*
+                CPU does not know how to write this register, pass it to the
+                device/board
+            */
+            cpu_physical_memory_write(PHYS_BASE_REGS + port
+                                              + AVR_CPU_IO_REGS_BASE, &data, 
1);
+        }
+    }
+
+    /*  make a copy */
+    if (port < AVR_CPU_IO_REGS) {
+        env->io[port] = data;
+    }
+}
+
+/*
+    this function implements LD instruction when there is a posibility to read
+    from a CPU register
+*/
+target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
+{
+    uint8_t data;
+    switch (addr) {
+        /*  CPU registers */
+        case AVR_CPU_REGS_BASE ... AVR_CPU_REGS_LAST: {
+            data = env->r[addr - AVR_CPU_REGS_BASE];
+            break;
+        }
+        /*  CPU IO registers & EXT IO registers */
+        case AVR_CPU_IO_REGS_BASE ... AVR_EXT_IO_REGS_LAST: {
+            data = helper_inb(env, addr);
+            break;
+        }
+
+        /*  memory */
+        default: {
+            cpu_physical_memory_read(PHYS_BASE_DATA + addr - VIRT_BASE_DATA,
+                                                                      &data, 
1);
+        }
+    }
+
+    env->fullacc = false;
+
+    return  data;
+}
+
+/*
+    this function implements LD instruction when there is a posibility to write
+    into a CPU register
+*/
+void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
+{
+    switch (addr) {
+        /*  CPU registers */
+        case AVR_CPU_REGS_BASE ... AVR_CPU_REGS_LAST: {
+            env->r[addr - AVR_CPU_REGS_BASE] = data;
+            break;
+        }
+
+        /*  CPU IO registers & EXT IO registers */
+        case AVR_CPU_IO_REGS_BASE ... AVR_EXT_IO_REGS_LAST: {
+            helper_outb(env, data, addr);
+            break;
+        }
+
+        /*  memory */
+        default: {
+            cpu_physical_memory_write(PHYS_BASE_DATA + addr - VIRT_BASE_DATA,
+                                                                      &data, 
1);
+        }
+    }
+
+    env->fullacc = false;
+}
+
diff --git a/target-avr/helper.h b/target-avr/helper.h
index c60ac3e..6036315 100644
--- a/target-avr/helper.h
+++ b/target-avr/helper.h
@@ -18,5 +18,11 @@
  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  */
 
+DEF_HELPER_1(wdr, void, env)
 DEF_HELPER_1(debug, void, env)
-
+DEF_HELPER_1(sleep, void, env)
+DEF_HELPER_1(unsupported, void, env)
+DEF_HELPER_3(outb, void, env, i32, i32)
+DEF_HELPER_2(inb, tl, env, i32)
+DEF_HELPER_3(fullwr, void, env, i32, i32)
+DEF_HELPER_2(fullrd, tl, env, i32)
diff --git a/target-avr/translate.c b/target-avr/translate.c
index ce87c11..a7fbe3d 100644
--- a/target-avr/translate.c
+++ b/target-avr/translate.c
@@ -152,6 +152,14 @@ void gen_intermediate_code(CPUAVRState *env, struct 
TranslationBlock *tb)
     if (max_insns > TCG_MAX_INSNS) {
         max_insns = TCG_MAX_INSNS;
     }
+    if (tb->flags & TB_FLAGS_FULL_ACCESS) {
+        /*
+            this flag is set by ST/LD instruction
+            we will regenerate ONLY it with mem/cpu memory access
+            insttead of mem access
+        */
+        max_insns = 1;
+    }
 
     gen_tb_start(tb);
 
@@ -222,6 +230,7 @@ void gen_intermediate_code(CPUAVRState *env, struct 
TranslationBlock *tb)
     }
 
 done_generating:
+    env->fullacc = false;
     gen_tb_end(tb, num_insns);
 
     tb->size = (npc - pc_start) * 2;
-- 
2.4.9 (Apple Git-60)