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[Qemu-devel] [PATCH 14/32] ppc: Don't update NIP in lmw/stmw/icbi
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-devel] [PATCH 14/32] ppc: Don't update NIP in lmw/stmw/icbi |
Date: |
Wed, 27 Jul 2016 08:21:08 +1000 |
Instead, pass GETPC() result to the corresponding helpers.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/mem_helper.c | 11 ++++++-----
target-ppc/translate.c | 6 ------
2 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index de96c91..e20a53e 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -57,9 +57,9 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t
reg)
{
for (; reg < 32; reg++) {
if (needs_byteswap(env)) {
- env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
+ env->gpr[reg] = bswap32(cpu_ldl_data_ra(env, addr, GETPC()));
} else {
- env->gpr[reg] = cpu_ldl_data(env, addr);
+ env->gpr[reg] = cpu_ldl_data_ra(env, addr, GETPC());
}
addr = addr_add(env, addr, 4);
}
@@ -69,9 +69,10 @@ void helper_stmw(CPUPPCState *env, target_ulong addr,
uint32_t reg)
{
for (; reg < 32; reg++) {
if (needs_byteswap(env)) {
- cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
+ cpu_stl_data_ra(env, addr, bswap32((uint32_t)env->gpr[reg]),
+ GETPC());
} else {
- cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
+ cpu_stl_data_ra(env, addr, (uint32_t)env->gpr[reg], GETPC());
}
addr = addr_add(env, addr, 4);
}
@@ -178,7 +179,7 @@ void helper_icbi(CPUPPCState *env, target_ulong addr)
* (not a fetch) by the MMU. To be sure it will be so,
* do the load "by hand".
*/
- cpu_ldl_data(env, addr);
+ cpu_ldl_data_ra(env, addr, GETPC());
}
/* XXX: to be tested */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9d2e923..c4f8916 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2654,8 +2654,6 @@ static void gen_lmw(DisasContext *ctx)
TCGv t0;
TCGv_i32 t1;
gen_set_access_type(ctx, ACCESS_INT);
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rD(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
@@ -2670,8 +2668,6 @@ static void gen_stmw(DisasContext *ctx)
TCGv t0;
TCGv_i32 t1;
gen_set_access_type(ctx, ACCESS_INT);
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
t0 = tcg_temp_new();
t1 = tcg_const_i32(rS(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
@@ -3872,8 +3868,6 @@ static void gen_icbi(DisasContext *ctx)
{
TCGv t0;
gen_set_access_type(ctx, ACCESS_CACHE);
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_icbi(cpu_env, t0);
--
2.7.4
- [Qemu-devel] [PATCH 28/32] ppc: Avoid double translation for lvx/lvxl/stvx/stvxl, (continued)
- [Qemu-devel] [PATCH 28/32] ppc: Avoid double translation for lvx/lvxl/stvx/stvxl, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 29/32] ppc: Don't set access_type on all load/stores on hash64, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 30/32] ppc: Use a helper to generate "LE unsupported" alignment interrupts, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 22/32] ppc: Don't update NIP if not taking alignment exceptions, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 26/32] ppc: Speed up dcbz, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 32/32] ppc: Speed up load/store multiple, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 14/32] ppc: Don't update NIP in lmw/stmw/icbi,
Benjamin Herrenschmidt <=
- [Qemu-devel] [PATCH 23/32] ppc: Don't update NIP in dcbz and lscbx, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 17/32] ppc: Fix source NIP on SLB related interrupts, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-devel] [PATCH 25/32] ppc: Handle unconditional (always/never) traps at translation time, Benjamin Herrenschmidt, 2016/07/26
- Re: [Qemu-devel] [PATCH 01/32] ppc: Fix fault PC reporting for lve*/stve* VMX instructions, David Gibson, 2016/07/26