Re: [Qemu-devel] [PATCH 12/32] ppc: FP exceptions are always precise

[Benjamin Herrenschmidt]

On Wed, 2016-07-27 at 12:00 +1000, David Gibson wrote:
> On Wed, Jul 27, 2016 at 08:21:06AM +1000, Benjamin Herrenschmidt
> wrote:
> > 
> > We don't implement imprecise FP exceptions and using store_current
> > which sets SRR1 to the *previous* instruction never makes sense
> > for these. So let's be truthful and make them precise, which is
> > allowed by the architecture.
> 
> I don't see any store_correct in the altered code, so the description
> doesn't quite make sense to me.

The existing program check default to store_current. We want
store_next.

The labels are misnamed, I fix that in a subsequent patch.
store_current means use the "current" ctx->nip which is usually
pointing to the *next* instruction ;-) (though not always).

It's all very messy and fixing that is  what a susequent patch in the
series does.

> > 
> > 
> > Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> > ---
> >  target-ppc/excp_helper.c | 11 ++++++-----
> >  target-ppc/translate.c   |  1 -
> >  2 files changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> > index f4b115e..91fdf4b 100644
> > --- a/target-ppc/excp_helper.c
> > +++ b/target-ppc/excp_helper.c
> > @@ -274,12 +274,13 @@ static inline void powerpc_excp(PowerPCCPU
> > *cpu, int excp_model, int excp)
> >                  env->error_code = 0;
> >                  return;
> >              }
> > +
> > +            /* FP exceptions always have NIP pointing to the
> > faulting
> > +             * instruction, so always use store_next and claim we
> > are
> > +             * precise in the MSR.
> > +             */
> >              msr |= 0x00100000;
> > -            if (msr_fe0 == msr_fe1) {
> > -                goto store_next;
> > -            }
> > -            msr |= 0x00010000;
> > -            break;
> > +            goto store_next;
> >          case POWERPC_EXCP_INVAL:
> >              LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n",
> > env->nip);
> >              msr |= 0x00080000;
> > diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> > index cb4e313..a05fed7 100644
> > --- a/target-ppc/translate.c
> > +++ b/target-ppc/translate.c
> > @@ -2846,7 +2846,6 @@ static void
> > gen_conditional_store(DisasContext *ctx, TCGv EA,
> >                                    int reg, int size)
> >  {
> >      TCGv t0 = tcg_temp_new();
> > -    uint32_t save_exception = ctx->exception;
> 
> Also, this appears to be an unrelated change.
> 
> > 
> >      tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
> >      tcg_gen_movi_tl(t0, (size << 5) | reg);
>