Re: [Qemu-devel] [PATCH] target-i386: add more Intel AVX-512 instructions support

[Eduardo Habkost]

On Tue, Aug 02, 2016 at 04:10:39PM +0800, Luwei Kang wrote:
> Add more AVX512 feature bits, include AVX512DQ, AVX512IFMA,
> AVX512BW, AVX512VL, AVX512VBMI. Its spec can be found at:
> https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf
> 
> Signed-off-by: Luwei Kang <address@hidden>

As we're past hard freeze, I queued it for 2.8. Thanks.

> ---
>  target-i386/cpu.c | 14 +++++++++-----
>  target-i386/cpu.h |  5 +++++
>  2 files changed, 14 insertions(+), 5 deletions(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 6a1afab..ec674dc 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -298,14 +298,18 @@ static const char *svm_feature_name[] = {
>  };
>  
>  static const char *cpuid_7_0_ebx_feature_name[] = {
> -    "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
> -    "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
> -    "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
> -    "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
> +    "fsgsbase", "tsc_adjust", NULL, "bmi1",
> +    "hle", "avx2", NULL, "smep",
> +    "bmi2", "erms", "invpcid", "rtm",
> +    NULL, NULL, "mpx", NULL,
> +    "avx512f", "avx512dq", "rdseed", "adx",
> +    "smap", "avx512ifma", "pcommit", "clflushopt",
> +    "clwb", NULL, "avx512pf", "avx512er",
> +    "avx512cd", NULL, "avx512bw", "avx512vl",
>  };
>  
>  static const char *cpuid_7_0_ecx_feature_name[] = {
> -    NULL, NULL, "umip", "pku",
> +    NULL, "avx512vbmi", "umip", "pku",
>      "ospke", NULL, NULL, NULL,
>      NULL, NULL, NULL, NULL,
>      NULL, NULL, NULL, NULL,
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 65615c0..cf14bcb 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -606,16 +606,21 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>  #define CPUID_7_0_EBX_RTM      (1U << 11)
>  #define CPUID_7_0_EBX_MPX      (1U << 14)
>  #define CPUID_7_0_EBX_AVX512F  (1U << 16) /* AVX-512 Foundation */
> +#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword 
> Instrs */
>  #define CPUID_7_0_EBX_RDSEED   (1U << 18)
>  #define CPUID_7_0_EBX_ADX      (1U << 19)
>  #define CPUID_7_0_EBX_SMAP     (1U << 20)
> +#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused 
> Multiply Add */
>  #define CPUID_7_0_EBX_PCOMMIT  (1U << 22) /* Persistent Commit */
>  #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized 
> */
>  #define CPUID_7_0_EBX_CLWB     (1U << 24) /* Cache Line Write Back */
>  #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
>  #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and 
> Reciprocal */
>  #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
> +#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word 
> Instructions */
> +#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length 
> Extensions */
>  
> +#define CPUID_7_0_ECX_VBMI     (1U << 1)  /* AVX-512 Vector Byte 
> Manipulation Instrs */
>  #define CPUID_7_0_ECX_UMIP     (1U << 2)
>  #define CPUID_7_0_ECX_PKU      (1U << 3)
>  #define CPUID_7_0_ECX_OSPKE    (1U << 4)
> -- 
> 2.7.4
> 

-- 
Eduardo