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Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU


From: Valentine Sinitsyn
Subject: Re: [Qemu-devel] [V15 3/4] hw/i386: Introduce AMD IOMMU
Date: Sat, 13 Aug 2016 00:41:51 +0500
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0

On 13.08.2016 00:40, David Kiarie wrote:


On Fri, Aug 12, 2016 at 10:10 PM, Valentine Sinitsyn
<address@hidden <mailto:address@hidden>> wrote:

    Hi David,

    On 02.08.2016 13:39, David Kiarie wrote:

        Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU.
        The IOMMU does basic translation, error checking and has a
        minimal IOTLB implementation. This IOMMU bypassed the need
        for target aborts by responding with IOMMU_NONE access rights
        and exempts the region 0xfee00000-0xfeefffff from translation
        as it is the q35 interrupt region.

        We advertise features that are not yet implemented to please
        the Linux IOMMU driver.

        IOTLB aims at implementing commands on real IOMMUs which is
        essential for debugging and may not offer any performance
        benefits

        Signed-off-by: David Kiarie <address@hidden
        <mailto:address@hidden>>
        ---
        +
        +/* IRTE size with GASup enabled */
        +#define AMDVI_IRTE_SIZE_GASUP   0x10
        +
        +#define AMDVI_IRTE_VECTOR_MASK    (0xffU << 16)
        +#define AMDVI_IRTE_DEST_MASK      (0xffU << 8)
        +#define AMDVI_IRTE_DM_MASK        (0x1U << 6)
        +#define AMDVI_IRTE_RQEOI_MASK     (0x1U << 5)
        +#define AMDVI_IRTE_INTTYPE_MASK   (0x7U << 2)
        +#define AMDVI_IRTE_SUPIOPF_MASK   (0x1U << 1)
        +#define AMDVI_IRTE_REMAP_MASK     (0x1U << 0)
        +
        +#define AMDVI_IR_TABLE_SIZE_MASK 0xfe
        +
        +/* offsets into MSI data */
        +#define AMDVI_MSI_DATA_DM_RSHIFT       0x8
        +#define AMDVI_MSI_DATA_LEVEL_RSHIFT    0xe
        +#define AMDVI_MSI_DATA_TRM_RSHIFT      0xf
        +
        +/* offsets into MSI address */
        +#define AMDVI_MSI_ADDR_DM_RSHIFT       0x2
        +#define AMDVI_MSI_ADDR_RH_RSHIFT       0x3
        +#define AMDVI_MSI_ADDR_DEST_RSHIFT     0xc
        +
        +#define AMDVI_LOCAL_APIC_ADDR     0xfee00000
        +
        +/* extended feature support */
        +#define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH |
        AMDVI_FEATURE_PPR | \
        +        AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_GA | \



    Came across this when reviewing your IR series.
    Do you really support Guest Translation in your code? I'm also not
    sure if QEMU emulates Virtual APIC. So I'd skip the last two bits.


You mean GT and GA ? I could do a bit more research about GA but as I
have mentioned in the commit message the Linux AMD-Vi (which is the
primary target) checks for some of these features when deciding the
version of this IOMMU otherwise it defaults to IOMMU version 1.
True. Ignore this comment then.

Valentine



    Valentine


        +        AMDVI_FEATURE_HE | AMDVI_GATS_MODE | AMDVI_HATS_MODE)
        +
        +/* capabilities header */
        +#define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \
        +        AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \
        +        | AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \
        +        AMDVI_CAPAB_FLAG_HTTUNNEL |  AMDVI_CAPAB_EFR_SUP)
        +
        +/* AMDVI default address */
        +#define AMDVI_BASE_ADDR 0xfed80000







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