Re: [Qemu-devel] a question

[Peter Maydell]

On 26 August 2016 at 10:31, Michael Rolnik <address@hidden> wrote:
> I want to partially implement AT STK500 board  in order to run FreeRTOS AVR
> / ATMegaAVR demo.
> if you look into ATmega32 documentation you will see that, for example,
> Timer/Countet1 registers are held together at memory addresses [0x46 ..
> 0xff], but interrupt masks and enable bits are at some other place, actually
> 0x58 .. 0x59.

(0x58..0x59 is a subset of 0x46..0xff -- I think from the docs
that you meant 0x46..0x4f.)

I think I would treat this set of timers as a single device that
implements all the timers, and which implements also the timer
interrupt mask/enable registers. Where there are multiple disjoint
register sets you can do this by having the device provide multiple
MemoryRegions, which the SoC container device then maps into the
memory space at the right places.

If you plan to support multiple CPUs which reuse some of the
individual timer modules but not all of them, you can structure
the code to allow convenient reuse, but that is an internal
detail of the overall "timers" device.

> create non memory mapped devices. Each device will export the following
> functions
>
> avr_<device>_init
> avr_<device>_read_<register>
> avr_<device>_write_<register>
>
> create "big" memory mapped device, which will cover the whole IO space and
> it will call _read_/_write_ functions of the devices when there is an access
> to specific address in the IO memory space.

You can do all this with the memory region API. Your various
devices can provide multiple memory regions (implementing the bits
of memory space that they care about), and then a higher level
SoC container device can map those into the right places in a
container memory region which it then exports to the board level.
You don't need to invent a new API for having devices provide registers.

thanks
-- PMM