Re: [Qemu-devel] [PATCH RFC v1 02/29] target-arc: ADC, ADD, ADD1, ADD2, ADD3

[Richard Henderson]

On 09/08/2016 03:31 PM, Michael Rolnik wrote:
> Signed-off-by: Michael Rolnik <address@hidden>
> ---
>  target-arc/Makefile.objs    |   1 +
>  target-arc/translate-inst.c | 170 
> ++++++++++++++++++++++++++++++++++++++++++++
>  target-arc/translate-inst.h |  30 ++++++++
>  3 files changed, 201 insertions(+)
>  create mode 100644 target-arc/translate-inst.c
>  create mode 100644 target-arc/translate-inst.h

Please don't split translate.c into translate-inst.* and decode.c like you did
for AVR.  Since you're not generating any source from a template, there's even
less call for it here than before.

> +static void gen_add_Cf(TCGv dest, TCGv src1, TCGv src2)
> +{
> +    TCGv t1 = tcg_temp_new_i32();
> +    TCGv t2 = tcg_temp_new_i32();
> +    TCGv t3 = tcg_temp_new_i32();
> +
> +    tcg_gen_and_tl(t1, src1, src2); /*  t1 = src1 & src2                    
> */
> +    tcg_gen_andc_tl(t2, src1, dest);/*  t2 = src1 & ~dest                   
> */
> +    tcg_gen_andc_tl(t3, src2, dest);/*  t3 = src2 & ~dest                   
> */
> +    tcg_gen_or_tl(t1, t1, t2);      /*  t1 = t1 | t2 | t3                   
> */
> +    tcg_gen_or_tl(t1, t1, t3);
> +
> +    tcg_gen_shri_tl(cpu_Cf, t1, 31);/*  Cf = t1(31)                         
> */

I've shown you before how to generate a carry bit from tcg_gen_add2_tl.

> +int arc_gen_ADC(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
> +{
> +    TCGv rslt = dest;
> +
> +    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
> +        rslt = tcg_temp_new_i32();
> +    }

It would be cleaner to simply always use a temporary.  The tcg optimizer will
generate the same code either way.


r~