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Re: [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, F
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions, |
Date: |
Tue, 27 Sep 2016 12:20:12 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 |
On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +/* adapted from Spike's decode.h:set_fp_exceptions */
> +#define set_fp_exceptions() do { \
> + env->csr[CSR_FFLAGS] |=
> softfloat_flags_to_riscv(get_float_exception_flags(\
> + &env->fp_status)); \
> + set_float_exception_flags(0, &env->fp_status); \
> +} while (0)
> +
> +uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
> + uint64_t frs3, uint64_t rm)
> +{
> + set_float_rounding_mode(RM, &env->fp_status);
> + frs1 = float32_muladd(frs1, frs2, frs3, 0, &env->fp_status);
> + set_fp_exceptions();
> + return frs1;
> +}
I should also mention that I think it would be preferable to canonically store
the fflags csr in fp_status. This means that you only need to perform this
flags conversion when reading or writing the csr, and not upon every fp insn.
The conversion of bits at each fp insn is done on other targets in order to
notice when exceptions must be taken. Since riscv has no fp exceptions, this
isn't a factor.
r~
[Qemu-devel] [PATCH 13/18] target-riscv: Add CSR read/write helpers, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,, Sagar Karandikar, 2016/09/26
- Re: [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,, Richard Henderson, 2016/09/26
- Re: [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,,
Richard Henderson <=
[Qemu-devel] [PATCH 05/18] target-riscv: Add Arithmetic instructions, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 18/18] target-riscv: Add generic test board, activate target, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 11/18] target-riscv: Add Double Precision Floating-Point Instructions, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode, Sagar Karandikar, 2016/09/26
[Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/, Sagar Karandikar, 2016/09/26