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[Qemu-devel] [PULL 05/25] aspeed: move the flash module mapping address
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/25] aspeed: move the flash module mapping address under the controller definition |
Date: |
Mon, 17 Oct 2016 19:40:24 +0100 |
From: Cédric Le Goater <address@hidden>
This will ease the definition of the new controllers for the AST2500
SoC and also ease the support of the segment registers, which provide
a way to reconfigure the mapping window of each slave.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/aspeed_soc.c | 9 ++++-----
hw/ssi/aspeed_smc.c | 15 +++++++++++----
include/hw/ssi/aspeed_smc.h | 3 ++-
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 479c0d2..80ad732 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -31,9 +31,6 @@
#define ASPEED_SOC_TIMER_BASE 0x1E782000
#define ASPEED_SOC_I2C_BASE 0x1E78A000
-#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
-#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
-
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
@@ -187,7 +184,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, ASPEED_SOC_FMC_FLASH_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
+ s->fmc.ctrl->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
qdev_get_gpio_in(DEVICE(&s->vic), 19));
@@ -200,7 +198,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 0, ASPEED_SOC_SPI_BASE);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, ASPEED_SOC_SPI_FLASH_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1,
+ s->spi.ctrl->flash_window_base);
/* SDMC - SDRAM Memory Controller */
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index d319e04..84c1829 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -127,6 +127,10 @@
#define R_SPI_MISC_CTRL (0x10 / 4)
#define R_SPI_TIMINGS (0x14 / 4)
+#define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
+#define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
+#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
+
/*
* Default segments mapping addresses and size for each slave per
* controller. These can be changed when board is initialized with the
@@ -151,11 +155,14 @@ static const AspeedSegments aspeed_segments_spi[] = {
static const AspeedSMCController controllers[] = {
{ "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
- CONF_ENABLE_W0, 5, aspeed_segments_legacy, 0x6000000 },
+ CONF_ENABLE_W0, 5, aspeed_segments_legacy,
+ ASPEED_SOC_SMC_FLASH_BASE, 0x6000000 },
{ "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS,
- CONF_ENABLE_W0, 5, aspeed_segments_fmc, 0x10000000 },
+ CONF_ENABLE_W0, 5, aspeed_segments_fmc,
+ ASPEED_SOC_FMC_FLASH_BASE, 0x10000000 },
{ "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS,
- SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, 0x10000000 },
+ SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi,
+ ASPEED_SOC_SPI_FLASH_BASE, 0x10000000 },
};
static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
@@ -395,7 +402,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error
**errp)
memory_region_init_io(&s->mmio_flash, OBJECT(s),
&aspeed_smc_flash_default_ops, s, name,
- s->ctrl->mapping_window_size);
+ s->ctrl->flash_window_size);
sysbus_init_mmio(sbd, &s->mmio_flash);
s->flashes = g_new0(AspeedSMCFlash, s->num_cs);
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index def3b45..bdfbcc0 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -42,7 +42,8 @@ typedef struct AspeedSMCController {
uint8_t conf_enable_w0;
uint8_t max_slaves;
const AspeedSegments *segments;
- uint32_t mapping_window_size;
+ hwaddr flash_window_base;
+ uint32_t flash_window_size;
} AspeedSMCController;
typedef struct AspeedSMCFlash {
--
2.7.4
- [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 13/25] hw/arm/virt-acpi-build: fix MADT generation, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 12/25] hw/intc/arm_gic_kvm: Fix build on aarch64, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 10/25] hw/arm/boot: allow using a command line specified dtb without a kernel, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 08/25] aspeed: create mapping regions for the maximum number of slaves, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 20/25] target-arm: Comments added to identify cases in a switch, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 05/25] aspeed: move the flash module mapping address under the controller definition,
Peter Maydell <=
- [Qemu-devel] [PULL 04/25] aspeed: rename the smc object to fmc, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 24/25] hw/intc/arm_gicv3: Fix ICC register tracepoints, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 02/25] Reducing stack frame size in stream_process_mem2s(), Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 14/25] hw/arm/virt: no ITS on older machine types, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 15/25] tests: add a m25p80 test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 21/25] Fix masking of PC lower bits when doing exception returns, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 19/25] target-arm: Code changes to implement overwrite of tag field on PC load, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 01/25] docs/generic-loader: Update the document, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1), Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 17/25] pxa2xx: Auto-assign name for i2c bus in i2c_init_bus., Peter Maydell, 2016/10/17