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[Qemu-devel] [PATCH v2 05/17] target-m68k: add dbcc
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH v2 05/17] target-m68k: add dbcc |
Date: |
Thu, 27 Oct 2016 02:42:18 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index e595673..1836a22 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1105,6 +1105,30 @@ DISAS_INSN(scc)
tcg_temp_free(tmp);
}
+DISAS_INSN(dbcc)
+{
+ TCGLabel *l1;
+ TCGv reg;
+ TCGv tmp;
+ int16_t offset;
+ uint32_t base;
+
+ reg = DREG(insn, 0);
+ base = s->pc;
+ offset = (int16_t)read_im16(env, s);
+ l1 = gen_new_label();
+ gen_jmpcc(s, (insn >> 8) & 0xf, l1);
+
+ tmp = tcg_temp_new();
+ tcg_gen_ext16s_i32(tmp, reg);
+ tcg_gen_addi_i32(tmp, tmp, -1);
+ gen_partset_reg(OS_WORD, reg, tmp);
+ tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
+ gen_jmp_tb(s, 1, base + offset);
+ gen_set_label(l1);
+ gen_jmp_tb(s, 0, s->pc);
+}
+
DISAS_INSN(undef_mac)
{
gen_exception(s, s->pc - 2, EXCP_LINEA);
@@ -3137,6 +3161,7 @@ void register_m68k_insns (CPUM68KState *env)
INSN(addsubq, 5080, f0c0, M68000);
INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
+ INSN(dbcc, 50c8, f0f8, M68000);
INSN(addsubq, 5080, f1c0, CF_ISA_A);
INSN(tpf, 51f8, fff8, CF_ISA_A);
--
2.7.4
- [Qemu-devel] [PATCH v2 00/17] 680x0 instruction set, part 1, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 02/17] target-m68k: add linkl, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 03/17] target-m68k: add exg ops, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 01/17] target-m68k: add bkpt instruction, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 07/17] target-m68k: add addressing modes to not, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 05/17] target-m68k: add dbcc,
Laurent Vivier <=
- [Qemu-devel] [PATCH v2 06/17] target-m68k: Inline addx, subx, negx, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 08/17] target-m68k: eor can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 09/17] target-m68k: or can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 04/17] target-m68k: add addressing modes to scc, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 10/17] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 16/17] target-m68k: cmp manages word and bytes operands, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 14/17] target-m68k: add addressing modes to neg, Laurent Vivier, 2016/10/26
- [Qemu-devel] [PATCH v2 17/17] target-m68k: immediate ops manage word and byte operands, Laurent Vivier, 2016/10/26