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| From: | Richard Henderson |
| Subject: | Re: [Qemu-devel] [PATCH v2] target-sh4: add atomic tas |
| Date: | Thu, 3 Nov 2016 13:15:03 -0600 |
| User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 |
On 11/03/2016 11:52 AM, Paolo Bonzini wrote:
UP kernel = no sane way to implement this in user-mode qemu?
Probably no straight-forward way, no.
Another possibility is to treat the load as a LL and the store as a SC (implemented in turn with cmpxchg+branch if it fails). cmpxchg spans two basic blocks, so maybe one also needs to look at r0 and sp in cpu_get_tb_cpu_state...
Yeah, that's a possibility. With the store-conditional failure auto-branching back to the start of the sequence (r0+sp).
Anyhow this patch seems like a bugfix.
Absolutely. r~
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