[Qemu-devel] [PATCH v6 00/19] Remaining MTTCG Base patches and ARM enablement

[Alex Bennée]

Hi,

A chunk of the MTTCG work was merged for 2.8 so this constitutes what
is left for the next cycle. The changes are minor except for a new
patch to reduce BQL contention on ARM during yield/wfi instructions.

I've also taken the time to update the design document which now
covers all the solutions for the various design requirements in the
document.

The one outstanding question is how to deal with the TLB flush
semantics of the various guest architectures. Currently flushes to
other vCPUs will happen at the end of their currently executing
Translation Block which could mean the originating vCPU makes
assumptions about flushes having been completed when they haven't. In
practice this hasn't been a problem and I haven't been able to
construct a test case so far that would fail in such a case. This is
probably because most tear downs of the other vCPU TLBs tend to be
done while the other vCPUs are not doing much. If anyone can come up
with a test case that would fail if this assumption isn't met then
please let me know.

We already have all the tools to meet these requirements if we want by
scheduling safe async work however this might slow things down if
these sort of flushes are frequent.

These patches apply cleanly on top of the current master. Please
review the code and I look forward to seeing other architectures
enable MTTCG on top of this series.

Alex Bennée (15):
  docs: new design document multi-thread-tcg.txt
  tcg: add kick timer for single-threaded vCPU emulation
  tcg: rename tcg_current_cpu to tcg_current_rr_cpu
  tcg: remove global exit_request
  tcg: enable tb_lock() for SoftMMU
  tcg: enable thread-per-vCPU
  cputlb: add assert_cpu_is_self checks
  cputlb: tweak qemu_ram_addr_from_host_nofail reporting
  cputlb: atomically update tlb fields used by tlb_reset_dirty
  target-arm/powerctl: defer cpu reset work to CPU context
  target-arm/cpu: don't reset TLB structures, use cputlb to do it
  target-arm: ensure BQL taken for ARM_CP_IO register access
  target-arm: helpers which may affect global state need the BQL
  target-arm: don't generate WFE/YIELD calls for MTTCG
  tcg: enable MTTCG by default for ARM on x86 hosts

Jan Kiszka (1):
  tcg: drop global lock during TCG code execution

KONRAD Frederic (2):
  tcg: add options for enabling MTTCG
  cputlb: introduce tlb_flush_* async work.

Pranith Kumar (1):
  tcg: handle EXCP_ATOMIC exception for system emulation

 configure                       |  12 ++
 cpu-exec-common.c               |   3 -
 cpu-exec.c                      |  37 ++--
 cpus.c                          | 314 ++++++++++++++++++++++++--------
 cputlb.c                        | 386 +++++++++++++++++++++++++++++++---------
 default-configs/arm-softmmu.mak |   2 +
 docs/multi-thread-tcg.txt       | 343 +++++++++++++++++++++++++++++++++++
 exec.c                          |  12 +-
 hw/core/irq.c                   |   1 +
 hw/i386/kvmvapic.c              |   4 +-
 hw/intc/arm_gicv3_cpuif.c       |   3 +
 hw/ppc/spapr.c                  |   3 +
 include/exec/cputlb.h           |   2 -
 include/exec/exec-all.h         |   5 +-
 include/qom/cpu.h               |  16 ++
 include/sysemu/cpus.h           |   2 +
 memory.c                        |   2 +
 qemu-options.hx                 |  20 +++
 qom/cpu.c                       |  10 ++
 target-arm/arm-powerctl.c       | 144 +++++++++------
 target-arm/cpu.c                |   6 +
 target-arm/helper.c             |   6 +
 target-arm/op_helper.c          |  50 +++++-
 target-arm/translate-a64.c      |   8 +-
 target-arm/translate.c          |  20 ++-
 target-i386/smm_helper.c        |   7 +
 target-s390x/misc_helper.c      |   5 +-
 translate-all.c                 |  27 ++-
 translate-common.c              |  21 +--
 vl.c                            |  49 ++++-
 30 files changed, 1241 insertions(+), 279 deletions(-)
 create mode 100644 docs/multi-thread-tcg.txt

-- 
2.10.1