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[Qemu-devel] [PATCH v4 29/64] target-microblaze: Use clz opcode
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 29/64] target-microblaze: Use clz opcode |
Date: |
Wed, 23 Nov 2016 14:01:26 +0100 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-microblaze/helper.h | 1 -
target-microblaze/op_helper.c | 5 -----
target-microblaze/translate.c | 2 +-
3 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/target-microblaze/helper.h b/target-microblaze/helper.h
index bd13826..71a6c08 100644
--- a/target-microblaze/helper.h
+++ b/target-microblaze/helper.h
@@ -3,7 +3,6 @@ DEF_HELPER_1(debug, void, env)
DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_2(cmp, i32, i32, i32)
DEF_HELPER_2(cmpu, i32, i32, i32)
-DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_3(divs, i32, env, i32, i32)
DEF_HELPER_3(divu, i32, env, i32, i32)
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 4a856e6..1e07e21 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -145,11 +145,6 @@ uint32_t helper_cmpu(uint32_t a, uint32_t b)
return t;
}
-uint32_t helper_clz(uint32_t t0)
-{
- return clz32(t0);
-}
-
uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
return compute_carry(a, b, cf);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index de2090a..0bb6095 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -768,7 +768,7 @@ static void dec_bit(DisasContext *dc)
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
- gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
+ tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32);
}
break;
case 0x1e0:
--
2.7.4
- [Qemu-devel] [PATCH v4 19/64] tcg/optimize: Fold movcond 0/1 into setcond, (continued)
- [Qemu-devel] [PATCH v4 19/64] tcg/optimize: Fold movcond 0/1 into setcond, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 18/64] target-s390x: Use the new deposit and extract ops, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 20/64] tcg: Add markup for output requires new register, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 22/64] tcg: Pass the opcode width to target_parse_constraint, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 21/64] tcg: Transition flat op_defs array to a target callback, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 25/64] disas/i386.c: Handle tzcnt, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 23/64] tcg: Allow an operand to be matching or a constant, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 26/64] disas/ppc: Handle popcnt and cnttz, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 24/64] tcg: Add clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 27/64] target-alpha: Use the ctz and clz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 29/64] target-microblaze: Use clz opcode,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 28/64] target-cris: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 31/64] target-openrisc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 30/64] target-mips: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 32/64] target-ppc: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 33/64] target-s390x: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 34/64] target-tilegx: Use clz and ctz opcodes, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 36/64] target-unicore32: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 35/64] target-tricore: Use clz opcode, Richard Henderson, 2016/11/23
- [Qemu-devel] [PATCH v4 38/64] target-arm: Use clz opcode, Richard Henderson, 2016/11/23