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Re: [Qemu-devel] [PATCH 01/23] target-arm: Log AArch64 exception returns
From: |
Andrew Jones |
Subject: |
Re: [Qemu-devel] [PATCH 01/23] target-arm: Log AArch64 exception returns |
Date: |
Tue, 20 Dec 2016 16:31:03 +0100 |
User-agent: |
Mutt/1.6.0.1 (2016-04-01) |
On Tue, Dec 13, 2016 at 10:36:02AM +0000, Peter Maydell wrote:
> We already log exception entry; add logging of the AArch64 exception
> return path as well.
>
> Signed-off-by: Peter Maydell <address@hidden>
> Reviewed-by: Edgar E. Iglesias <address@hidden>
> ---
> target-arm/op_helper.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index cd94216..ba796d8 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -17,6 +17,7 @@
> * License along with this library; if not, see
> <http://www.gnu.org/licenses/>.
> */
> #include "qemu/osdep.h"
> +#include "qemu/log.h"
> #include "cpu.h"
> #include "exec/helper-proto.h"
> #include "internals.h"
> @@ -972,6 +973,9 @@ void HELPER(exception_return)(CPUARMState *env)
> } else {
> env->regs[15] = env->elr_el[cur_el] & ~0x3;
> }
> + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
> + "AArch32 EL%d PC 0x%" PRIx32 "\n",
> + cur_el, new_el, env->regs[15]);
> } else {
> env->aarch64 = 1;
> pstate_write(env, spsr);
> @@ -980,6 +984,9 @@ void HELPER(exception_return)(CPUARMState *env)
> }
> aarch64_restore_sp(env, new_el);
> env->pc = env->elr_el[cur_el];
> + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
> + "AArch64 EL%d PC 0x%" PRIx64 "\n",
> + cur_el, new_el, env->pc);
> }
>
> arm_call_el_change_hook(arm_env_get_cpu(env));
> @@ -1002,6 +1009,8 @@ illegal_return:
> if (!arm_singlestep_active(env)) {
> env->pstate &= ~PSTATE_SS;
> }
> + qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: "
> + "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc);
> }
>
> /* Return true if the linked breakpoint entry lbn passes its checks */
> --
> 2.7.4
>
>
Should we output both the destination PC (ELR) and the source PC (where
the eret was)? Otherwise if there are many erets to the same entry point,
then the logs won't fully enlighten us.
Thanks,
drew
- Re: [Qemu-devel] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt, (continued)
- [Qemu-devel] [PATCH 07/23] hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 04/23] hw/arm/virt: add 2.9 machine type, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 02/23] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 09/23] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 05/23] hw/arm/virt: Merge VirtBoardInfo and VirtMachineState, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 01/23] target-arm: Log AArch64 exception returns, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 06/23] hw/arm/virt: Rename 'vbi' variables to 'vms', Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 12/23] target-arm: Add ARMCPU fields for GIC CPU i/f config, Peter Maydell, 2016/12/13
- [Qemu-devel] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2016/12/13