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[Qemu-devel] [PULL 06/25] hw/intc/arm_gicv3_common: fix aff3 in typer
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/25] hw/intc/arm_gicv3_common: fix aff3 in typer |
Date: |
Tue, 27 Dec 2016 15:20:58 +0000 |
From: Andrew Jones <address@hidden>
Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 0f8c4b8..0aa9b9c 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -204,7 +204,8 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
/* The CPU mp-affinity property is in MPIDR register format; squash
* the affinity bytes into 32 bits as the GICR_TYPER has them.
*/
- cpu_affid = (cpu_affid & 0xFF00000000ULL >> 8) | (cpu_affid &
0xFFFFFF);
+ cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) |
+ (cpu_affid & 0xFFFFFF);
s->cpu[i].gicr_typer = (cpu_affid << 32) |
(1 << 24) |
(i << 8) |
--
2.7.4
- [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 01/25] cadence_uart: Check baud rate generator and divider values on migration, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 02/25] cadence_uart: Check if receiver timeout counter is disabled, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 03/25] Correct value of ARM Cortex-A8 MVFR1 register., Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 04/25] target-arm: Fix aarch64 vec_reg_offset, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 05/25] target-arm: Fix aarch64 disas_ldst_single_struct, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 06/25] hw/intc/arm_gicv3_common: fix aff3 in typer,
Peter Maydell <=
- [Qemu-devel] [PULL 07/25] target-arm: Log AArch64 exception returns, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 08/25] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 09/25] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 10/25] hw/arm/virt: add 2.9 machine type, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 11/25] m25p80: add support for the mx66l1g45g, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 12/25] aspeed: QOMify the CPU object and attach it to the SoC, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 13/25] aspeed: remove cannot_destroy_with_object_finalize_yet, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 14/25] aspeed: attach the second SPI controller object to the SoC, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 15/25] aspeed: extend the board configuration with flash models, Peter Maydell, 2016/12/27
- [Qemu-devel] [PULL 16/25] aspeed: add support for the romulus-bmc board, Peter Maydell, 2016/12/27