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Re: [Qemu-devel] [PATCH v2 03/18] target-arm: Expose output GPIO line fo
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v2 03/18] target-arm: Expose output GPIO line for VCPU maintenance interrupt |
Date: |
Tue, 17 Jan 2017 13:50:29 -0800 |
On Mon, Jan 9, 2017 at 8:05 AM, Peter Maydell <address@hidden> wrote:
> The GICv3 support for virtualization includes an outbound
> maintenance interrupt signal which is asserted when the
> CPU interface wants to signal to the hypervisor that it
> needs attention. Expose this as an outbound GPIO line from
> the CPU object which can be wired up as a physical interrupt
> line by the board code (as we do already for the CPU timers).
>
> Signed-off-by: Peter Maydell <address@hidden>
> Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Thanks,
Alistair
> ---
> target/arm/cpu.h | 2 ++
> target/arm/cpu.c | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index ab119e6..764b511 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -555,6 +555,8 @@ struct ARMCPU {
> QEMUTimer *gt_timer[NUM_GTIMERS];
> /* GPIO outputs for generic timer */
> qemu_irq gt_timer_outputs[NUM_GTIMERS];
> + /* GPIO output for GICv3 maintenance interrupt signal */
> + qemu_irq gicv3_maintenance_interrupt;
>
> /* MemoryRegion to use for secure physical accesses */
> MemoryRegion *secure_memory;
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index f5cb30a..8932086 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -466,6 +466,9 @@ static void arm_cpu_initfn(Object *obj)
> arm_gt_stimer_cb, cpu);
> qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
> ARRAY_SIZE(cpu->gt_timer_outputs));
> +
> + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
> + "gicv3-maintenance-interrupt", 1);
> #endif
>
> /* DTB consumers generally don't in fact care what the 'compatible'
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57, (continued)
- [Qemu-devel] [PATCH v2 17/18] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 07/18] hw/intc/gicv3: Add data fields for virtualization support, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 06/18] hw/intc/gicv3: Add defines for ICH system register fields, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 05/18] target-arm: Add ARMCPU fields for GIC CPU i/f config, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 18/18] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 03/18] target-arm: Expose output GPIO line for VCPU maintenance interrupt, Peter Maydell, 2017/01/09
- Re: [Qemu-devel] [PATCH v2 03/18] target-arm: Expose output GPIO line for VCPU maintenance interrupt,
Alistair Francis <=
- [Qemu-devel] [PATCH v2 08/18] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 12/18] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 02/18] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 16/18] target/arm/psci.c: If EL2 implemented, start CPUs in EL2, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 13/18] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs, Peter Maydell, 2017/01/09
- [Qemu-devel] [PATCH v2 10/18] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers, Peter Maydell, 2017/01/09
- Re: [Qemu-devel] [Qemu-arm] [PATCH v2 00/18] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs, Peter Maydell, 2017/01/17