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[Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and w
From: |
Artyom Tarasenko |
Subject: |
[Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions |
Date: |
Wed, 18 Jan 2017 23:38:26 +0100 |
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/sparc/translate.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index a40c974..399a8ac 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -3468,7 +3468,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
rs1 = GET_FIELD(insn, 13, 17);
switch (rs1) {
case 0: // hpstate
- // gen_op_rdhpstate();
+ tcg_gen_ld_i64(cpu_dst, cpu_env,
+ offsetof(CPUSPARCState, hpstate));
break;
case 1: // htstate
// gen_op_rdhtstate();
@@ -4592,7 +4593,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
switch (rd) {
case 0: // hpstate
- // XXX gen_op_wrhpstate();
+ tcg_gen_st_i64(cpu_tmp0, cpu_env,
+ offsetof(CPUSPARCState,
+ hpstate));
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
--
2.7.2
- [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines, (continued)
- [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions,
Artyom Tarasenko <=
- [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs in hyperprivileged mode, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu, Artyom Tarasenko, 2017/01/18
- [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21), Artyom Tarasenko, 2017/01/18