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[Qemu-devel] [PULL 03/36] block: m25p80: Introduce die erase command
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/36] block: m25p80: Introduce die erase command |
Date: |
Thu, 19 Jan 2017 14:09:22 +0000 |
From: Marcin Krzeminski <address@hidden>
Modern big flash NOR devices consist of more than one die.
Some of them do not support chip erase and instead have a die
erase command that can erase one die only. This commit adds
support for defining the number of dies in the chip, and adds
support for die erase command.
The NOR flash model is not strict, so no option to
disable chip erase has been added.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/block/m25p80.c | 41 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 4ad67ac..74c6e39 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -74,6 +74,12 @@ typedef struct FlashPartInfo {
uint32_t n_sectors;
uint32_t page_size;
uint16_t flags;
+ /*
+ * Big sized spi nor are often stacked devices, thus sometime
+ * replace chip erase with die erase.
+ * This field inform how many die is in the chip.
+ */
+ uint8_t die_cnt;
} FlashPartInfo;
/* adapted from linux */
@@ -91,7 +97,8 @@ typedef struct FlashPartInfo {
.sector_size = (_sector_size),\
.n_sectors = (_n_sectors),\
.page_size = 256,\
- .flags = (_flags),
+ .flags = (_flags),\
+ .die_cnt = 0
#define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,
_flags)\
.part_name = _part_name,\
@@ -108,6 +115,24 @@ typedef struct FlashPartInfo {
.n_sectors = (_n_sectors),\
.page_size = 256,\
.flags = (_flags),\
+ .die_cnt = 0
+
+#define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
+ _flags, _die_cnt)\
+ .part_name = _part_name,\
+ .id = {\
+ ((_jedec_id) >> 16) & 0xff,\
+ ((_jedec_id) >> 8) & 0xff,\
+ (_jedec_id) & 0xff,\
+ ((_ext_id) >> 8) & 0xff,\
+ (_ext_id) & 0xff,\
+ },\
+ .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
+ .sector_size = (_sector_size),\
+ .n_sectors = (_n_sectors),\
+ .page_size = 256,\
+ .flags = (_flags),\
+ .die_cnt = _die_cnt
#define JEDEC_NUMONYX 0x20
#define JEDEC_WINBOND 0xEF
@@ -360,6 +385,8 @@ typedef enum {
REVCR = 0x65,
WEVCR = 0x61,
+
+ DIE_ERASE = 0xC4,
} FlashCMD;
typedef enum {
@@ -517,6 +544,16 @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
case BULK_ERASE:
len = s->size;
break;
+ case DIE_ERASE:
+ if (s->pi->die_cnt) {
+ len = s->size / s->pi->die_cnt;
+ offset = offset & (~(len - 1));
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
+ " by device\n");
+ return;
+ }
+ break;
default:
abort();
}
@@ -638,6 +675,7 @@ static void complete_collecting_data(Flash *s)
case ERASE4_32K:
case ERASE_SECTOR:
case ERASE4_SECTOR:
+ case DIE_ERASE:
flash_erase(s, s->cur_addr, s->cmd_in_progress);
break;
case WRSR:
@@ -884,6 +922,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case PP:
case PP4:
case PP4_4:
+ case DIE_ERASE:
s->needed_bytes = get_addr_length(s);
s->pos = 0;
s->len = 0;
--
2.7.4
- [Qemu-devel] [PULL 08/36] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function, (continued)
- [Qemu-devel] [PULL 08/36] aspeed/smc: remove call to aspeed_smc_update_cs() in reset function, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 29/36] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 20/36] hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 25/36] hw/intc/gicv3: Add data fields for virtualization support, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 19/36] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 26/36] hw/intc/arm_gicv3: Add accessors for ICH_ system registers, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 30/36] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update(), Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 18/36] hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 15/36] aspeed/smc: extend tests for Command mode, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 12/36] aspeed/smc: adjust the size of the register region, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 03/36] block: m25p80: Introduce die erase command,
Peter Maydell <=
- [Qemu-devel] [PULL 36/36] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 35/36] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 07/36] aspeed/smc: remove call to reset in realize function, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 04/36] block: m25p80: Improve 1GiB Micron flash definition, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 05/36] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32(), Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 02/36] block: m25p80: Add Quad Page Program 4byte, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 01/36] arm: Uniquely name imx25 I2C buses., Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 17/36] arm: virt: Fix segmentation fault when specifying an unsupported CPU, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 14/36] aspeed/smc: reset flash after each test, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 13/36] aspeed/smc: handle SPI flash Command mode, Peter Maydell, 2017/01/19