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[Qemu-devel] [PULL 14/36] aspeed/smc: reset flash after each test
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/36] aspeed/smc: reset flash after each test |
Date: |
Thu, 19 Jan 2017 14:09:33 +0000 |
From: Cédric Le Goater <address@hidden>
Let's make sure when each test is run that the flash object is in an
initial state and did not keep configuration from the previous tests.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
tests/m25p80-test.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/tests/m25p80-test.c b/tests/m25p80-test.c
index cb7ec81..8dd550d 100644
--- a/tests/m25p80-test.c
+++ b/tests/m25p80-test.c
@@ -50,6 +50,8 @@ enum {
READ = 0x03,
PP = 0x02,
WREN = 0x6,
+ RESET_ENABLE = 0x66,
+ RESET_MEMORY = 0x99,
EN_4BYTE_ADDR = 0xB7,
ERASE_SECTOR = 0xd8,
};
@@ -76,6 +78,14 @@ static void spi_conf(uint32_t value)
writel(ASPEED_FMC_BASE + R_CONF, conf);
}
+static void spi_conf_remove(uint32_t value)
+{
+ uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
+
+ conf &= ~value;
+ writel(ASPEED_FMC_BASE + R_CONF, conf);
+}
+
static void spi_ctrl_start_user(void)
{
uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
@@ -95,6 +105,18 @@ static void spi_ctrl_stop_user(void)
writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
}
+static void flash_reset(void)
+{
+ spi_conf(CONF_ENABLE_W0);
+
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
+ writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
+ spi_ctrl_stop_user();
+
+ spi_conf_remove(CONF_ENABLE_W0);
+}
+
static void test_read_jedec(void)
{
uint32_t jedec = 0x0;
@@ -108,6 +130,8 @@ static void test_read_jedec(void)
jedec |= readb(ASPEED_FLASH_BASE);
spi_ctrl_stop_user();
+ flash_reset();
+
g_assert_cmphex(jedec, ==, FLASH_JEDEC);
}
@@ -155,6 +179,8 @@ static void test_erase_sector(void)
for (i = 0; i < PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0xffffffff);
}
+
+ flash_reset();
}
static void test_erase_all(void)
@@ -182,6 +208,8 @@ static void test_erase_all(void)
for (i = 0; i < PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0xffffffff);
}
+
+ flash_reset();
}
static void test_write_page(void)
@@ -195,6 +223,7 @@ static void test_write_page(void)
spi_ctrl_start_user();
writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
+ writeb(ASPEED_FLASH_BASE, WREN);
writeb(ASPEED_FLASH_BASE, PP);
writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
@@ -215,6 +244,8 @@ static void test_write_page(void)
for (i = 0; i < PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0xffffffff);
}
+
+ flash_reset();
}
static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX";
--
2.7.4
- [Qemu-devel] [PULL 12/36] aspeed/smc: adjust the size of the register region, (continued)
- [Qemu-devel] [PULL 12/36] aspeed/smc: adjust the size of the register region, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 03/36] block: m25p80: Introduce die erase command, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 36/36] hw/arm/virt: Add board property to enable EL2, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 35/36] target-arm: Enable EL2 feature bit on A53 and A57, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 07/36] aspeed/smc: remove call to reset in realize function, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 04/36] block: m25p80: Improve 1GiB Micron flash definition, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 05/36] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32(), Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 02/36] block: m25p80: Add Quad Page Program 4byte, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 01/36] arm: Uniquely name imx25 I2C buses., Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 17/36] arm: virt: Fix segmentation fault when specifying an unsupported CPU, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 14/36] aspeed/smc: reset flash after each test,
Peter Maydell <=
- [Qemu-devel] [PULL 13/36] aspeed/smc: handle SPI flash Command mode, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 09/36] aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 11/36] aspeed/smc: unfold the AspeedSMCController array, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 06/36] target/arm: Implement DBGVCR32_EL2 system register, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 10/36] aspeed/smc: autostrap CE0/1 configuration, Peter Maydell, 2017/01/19
- [Qemu-devel] [PULL 16/36] aspeed: use first FMC flash as a boot ROM, Peter Maydell, 2017/01/19