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[Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code |
Date: |
Mon, 27 Feb 2017 18:04:52 +0000 |
M profile doesn't implement ARM, and the architecturally required
behaviour for attempts to execute with the Thumb bit clear is to
generate a UsageFault with the CFSR INVSTATE bit set. We were
incorrectly implementing this as generating an UNDEFINSTR UsageFault;
fix this.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
---
target/arm/cpu.h | 1 +
linux-user/main.c | 1 +
target/arm/helper.c | 4 ++++
target/arm/translate.c | 8 ++++++--
4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 045830a..9e7b2df 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -57,6 +57,7 @@
#define EXCP_VFIQ 15
#define EXCP_SEMIHOST 16 /* semihosting call */
#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
+#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
diff --git a/linux-user/main.c b/linux-user/main.c
index 9645122..10a3bb3 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -574,6 +574,7 @@ void cpu_loop(CPUARMState *env)
switch(trapnr) {
case EXCP_UDEF:
case EXCP_NOCP:
+ case EXCP_INVSTATE:
{
TaskState *ts = cs->opaque;
uint32_t opcode;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9081771..3f4211b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6245,6 +6245,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
break;
+ case EXCP_INVSTATE:
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
+ env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK;
+ break;
case EXCP_SWI:
/* The PC already points to the next instruction. */
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index abc1f77..b859f10 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7990,9 +7990,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
TCGv_i32 addr;
TCGv_i64 tmp64;
- /* M variants do not implement ARM mode. */
+ /* M variants do not implement ARM mode; this must raise the INVSTATE
+ * UsageFault exception.
+ */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
+ gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
+ default_exception_el(s));
+ return;
}
cond = insn >> 28;
if (cond == 0xf){
--
2.7.4
- [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions, (continued)
- [Qemu-devel] [PULL 21/30] armv7m: Extract "exception taken" code into functions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 24/30] armv7m: Allow SHCSR writes to change pending and active bits, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 17/30] armv7m: Escalate exceptions to HardFault if necessary, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 15/30] armv7m: Fix condition check for taking exceptions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 22/30] armv7m: Check exception return consistency, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 26/30] hw/sd: add card-reparenting function, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 16/30] arm: gic: Remove references to NVIC, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 01/30] target-arm: Implement BCM2835 hardware RNG, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 10/30] hw/arm/virt: Add a user option to disallow ITS instantiation, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 08/30] Add missing fp_access_check() to aarch64 crypto instructions, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code,
Peter Maydell <=
- [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke multi block transfer, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand(), Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer, Peter Maydell, 2017/02/27