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[Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negat
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx |
Date: |
Wed, 5 Apr 2017 14:41:44 +0200 |
From: Benjamin Herrenschmidt <address@hidden>
Under some circumstances, pci_intx() can return -1 (when the interrupt
pin in the config space is 0 which normally means no interrupt).
I have seen cases of pci_set_irq() being called on such devices, in
turn causing pci_irq_handler() to be called with "-1" as an argument
which doesn't seem like a terribly good idea.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: updated for qemu-2.9 ]
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/pci/pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 817ad14ed987..bfd65461348c 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1419,7 +1419,9 @@ qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
void pci_set_irq(PCIDevice *pci_dev, int level)
{
int intx = pci_intx(pci_dev);
- pci_irq_handler(pci_dev, intx, level);
+ if (intx >= 0) {
+ pci_irq_handler(pci_dev, intx, level);
+ }
}
/* Special hooks used by device assignment */
--
2.7.4
- [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator, (continued)
- [Qemu-devel] [PATCH 15/21] ppc/pnv: add initial IPMI sensors for the BMC simulator, Cédric Le Goater, 2017/04/05
- [Qemu-devel] [PATCH 16/21] ppc/pnv: generate an OEM SEL event on shutdown, Cédric Le Goater, 2017/04/05
- [Qemu-devel] [PATCH 17/21] qdev: Add a hook for a bus to device if it can add devices, Cédric Le Goater, 2017/04/05
- [Qemu-devel] [PATCH 18/21] pci: Use the new pci_can_add_device() to enforce devfn_min/max, Cédric Le Goater, 2017/04/05
- [Qemu-devel] [PATCH 19/21] pci: Don't call pci_irq_handler() for a negative intx,
Cédric Le Goater <=
- [Qemu-devel] [PATCH 21/21] ppc/pnv: Create a default PCI layout, Cédric Le Goater, 2017/04/05
[Qemu-devel] [PATCH 20/21] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge, Cédric Le Goater, 2017/04/05