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[Qemu-devel] [PATCH v2 3/9] target/openrisc: Fixes for memory debugging
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PATCH v2 3/9] target/openrisc: Fixes for memory debugging |
Date: |
Mon, 24 Apr 2017 07:40:51 +0900 |
When debugging in gdb you might want to inspect instructions in mapped
pages or in exception vectors like 0x800 etc. This was previously not
possible in qemu since the *get_phys_page_debug() routine only looked
into the data tlb.
Change to fall back to look into instruction tlb and plain physical
pages.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/mmu.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 56b11d3..a6d7bcd 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
{
int ret = TLBRET_MATCH;
- if (rw == 2) { /* ITLB */
+ if (rw == MMU_INST_FETCH) { /* ITLB */
*physical = 0;
ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
prot, address, rw);
@@ -221,12 +221,27 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs,
vaddr addr)
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
hwaddr phys_addr;
int prot;
+ int miss;
- if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
- return -1;
+ /* Check memory for any kind of address, since during debug the
+ gdb can ask for anything, check data tlb for address */
+ miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
+
+ /* Check instruction tlb */
+ if (miss) {
+ miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr,
MMU_INST_FETCH);
+ }
+
+ /* Last, fall back to a plain address */
+ if (miss) {
+ miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0);
}
- return phys_addr;
+ if (miss) {
+ return -1;
+ } else {
+ return phys_addr;
+ }
}
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
--
2.9.3
- [Qemu-devel] [PATCH v2 0/9] Openrisc misc features / fixes, Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 1/9] target/openrisc: Implement EVBAR register, Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 2/9] target/openrisc: Implement EPH bit, Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 3/9] target/openrisc: Fixes for memory debugging,
Stafford Horne <=
- [Qemu-devel] [PATCH v2 4/9] target/openrisc: add numcores and coreid support, Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 5/9] migration: Add VMSTATE_UINTTL_2DARRAY(), Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 6/9] target/openrisc: implement shadow registers, Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 7/9] migration: Add VMSTATE_STRUCT_2DARRAY(), Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 8/9] target/openrisc: Implement full vmstate serialization, Stafford Horne, 2017/04/23
- [Qemu-devel] [PATCH v2 9/9] target/openrisc: Remove duplicate features property, Stafford Horne, 2017/04/23
- Re: [Qemu-devel] [PATCH v2 0/9] Openrisc misc features / fixes, no-reply, 2017/04/23