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[Qemu-devel] [PATCH 4/9] Add risu_reginfo_ppc.h file
From: |
G 3 |
Subject: |
[Qemu-devel] [PATCH 4/9] Add risu_reginfo_ppc.h file |
Date: |
Mon, 24 Apr 2017 23:20:36 -0400 |
Add the risu_reginfo_ppc.h file. It defines the reginfo structure.
Signed-off-by: John Arbuckle <address@hidden>
---
risu_reginfo_ppc.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 risu_reginfo_ppc.h
diff --git a/risu_reginfo_ppc.h b/risu_reginfo_ppc.h
new file mode 100644
index 0000000..c3b342d
--- /dev/null
+++ b/risu_reginfo_ppc.h
@@ -0,0 +1,32 @@
+/******************************************
+ * File: risu_reginfo_ppc.h
+ * Description: 32 bit powerpc registers
+ * Date: 3-26-2017
+ ******************************************/
+
+#ifndef RISU_REGINFO_PPC_H
+#define RISU_REGINFO_PPC_H
+
+struct reginfo
+{
+ uint32_t faulting_insn;
+ uint32_t previous_instruction; /* The instruction before the
faulting instruction */
+ uint32_t second_previous_instruction; /* The second instruction
before the faulting instruction */
+
+ /************** User Model UISA *********************************/
+
+ uint32_t gpr[32]; /* General Purpose Registers */
+ double fpr[32]; /* Floating-point Registers */
+ uint32_t cr; /* Condition Register */
+ uint32_t fpscr; /* Floating-point Status and Control
Register */
+ uint32_t xer; /* Fixed-point Exception Register */
+ uint32_t lr; /* Link Register */
+ uint32_t ctr; /* Count Register */
+
+ /*
+ * Since we can't test any registers in the Supervisor Model,
they are not
+ * included.
+ */
+};
+
+#endif /* RISU_REGINFO_PPC_H */
--
2.10.2
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