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[Qemu-devel] [PULL 21/22] target/ppc: Allow workarounds for POWER9 DD1
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 21/22] target/ppc: Allow workarounds for POWER9 DD1 |
Date: |
Wed, 10 May 2017 17:01:14 +1000 |
POWER9 DD1 silicon has some bugs which mean it a) isn't really compliant
with the ISA v3.00 and b) require a number of special workarounds in the
kernel.
At the moment, qemu isn't aware of DD1. For TCG we don't really want it to
be (why bother emulating buggy silicon). But with KVM, the guest does need
to be aware of DD1 so it can apply the necessary workarounds.
Meanwhile, the feature negotiation between qemu and the guest strongly
favours architected compatibility modes to "raw" CPU modes. In combination
with the above, this means the guest sees architected POWER9 mode, and
doesn't apply the DD1 workarounds. Well, unless it has yet another
workaround to partially ignore what qemu tells it.
This patch addresses this by disabling support for compatibility modes when
using KVM on a POWER9 DD1 host.
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu-models.h | 1 +
target/ppc/kvm.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index d587e69..b563c45 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -561,6 +561,7 @@ enum {
CPU_POWERPC_POWER8NVL_BASE = 0x004C0000,
CPU_POWERPC_POWER8NVL_v10 = 0x004C0100,
CPU_POWERPC_POWER9_BASE = 0x004E0000,
+ CPU_POWERPC_POWER9_DD1 = 0x004E0100,
CPU_POWERPC_970_v22 = 0x00390202,
CPU_POWERPC_970FX_v10 = 0x00391100,
CPU_POWERPC_970FX_v20 = 0x003C0200,
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 8574c36..cb2cf2b 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2380,6 +2380,17 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc,
void *data)
#if defined(TARGET_PPC64)
pcc->radix_page_info = kvm_get_radix_page_info();
+
+ if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
+ /*
+ * POWER9 DD1 has some bugs which make it not really ISA 3.00
+ * compliant. More importantly, advertising ISA 3.00
+ * architected mode may prevent guests from activating
+ * necessary DD1 workarounds.
+ */
+ pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
+ | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
+ }
#endif /* defined(TARGET_PPC64) */
}
--
2.9.3
- [Qemu-devel] [PULL 02/22] target/ppc: Emulate LL/SC using cmpxchg helpers, (continued)
- [Qemu-devel] [PULL 02/22] target/ppc: Emulate LL/SC using cmpxchg helpers, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 18/22] target/ppc: Enable RADIX mmu mode for pseries TCG guest, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 16/22] target/ppc: Change tlbie invalid fields for POWER9 support, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 22/22] pnv: Fix build failures on some host platforms, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 11/22] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built as submodule, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 13/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 14/22] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 15/22] target/ppc: Update tlbie to check privilege level based on GTSE, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 01/22] ppc/pnv: restrict BMC object to the BMC simulator, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 19/22] ppc: xics: fix compilation with CentOS 6, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 21/22] target/ppc: Allow workarounds for POWER9 DD1,
David Gibson <=
- [Qemu-devel] [PULL 17/22] target/ppc: Implement ISA V3.00 radix page fault handler, David Gibson, 2017/05/10
- [Qemu-devel] [PULL 20/22] spapr: Don't accidentally advertise HTM support on POWER9, David Gibson, 2017/05/10
- Re: [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510, no-reply, 2017/05/10