[Qemu-devel] [PATCH v3 00/15] target/sh4: misc fixes, cleanup and optimizations

[Aurelien Jarno]

This patch series try to improve the SH4 target by using the (more or
less) recently introduced TCG features. It also fixes some issues spot
when writting the patches (linking of TB with different flags, SH4-A
specific instructions allowed on SH4) and correctly trap unaligned
accesses.

v3:
- Use extr instead of extrh/extrl in gen_store_fpr64, as suggested by
  Richard Henderson
- Use cpu_loop_exit_restore instead of cpu_loop_exit/cpu_restore_state
  in superh_cpu_do_unaligned_access
- Add a patch to convert the remaining cpu_loop_exit/cpu_restore_state
  to cpu_loop_exit_restore
- Add Reviewed-by entries

v2:
- Add some comments in the struct DisasContext declaration, as suggested
  by Philippe Mathieu-Daudé


Aurelien Jarno (15):
  target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags
  target/sh4: get rid of DELAY_SLOT_CLEARME
  target/sh4: do not include DELAY_SLOT_TRUE in the TB state
  target/sh4: move DELAY_SLOT_TRUE flag into a separate global
  target/sh4: fix BS_STOP exit
  target/sh4: fix BS_EXCP exit
  target/sh4: only save flags state at the end of the TB
  target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jump
  target/sh4: optimize gen_store_fpr64
  target/sh4: optimize gen_write_sr using extract op
  target/sh4: generate fences for SH4
  target/sh4: implement tas.b using atomic helper
  target/sh4: movua.l is an SH4-A only instruction
  target/sh4: trap unaligned accesses
  target/sh4: use cpu_loop_exit_restore

 target/sh4/cpu.c       |   1 +
 target/sh4/cpu.h       |  18 ++-
 target/sh4/helper.c    |   4 +-
 target/sh4/op_helper.c |  26 ++--
 target/sh4/translate.c | 322 +++++++++++++++++++++++--------------------------
 5 files changed, 181 insertions(+), 190 deletions(-)

-- 
2.11.0