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[Qemu-devel] [PATCH v2 13/27] target/sh4: Hoist fp register bank selecti
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 13/27] target/sh4: Hoist fp register bank selection |
Date: |
Thu, 6 Jul 2017 16:20:57 -1000 |
Compute which register bank to use once at the start of translation.
Signed-off-by: Richard Henderson <address@hidden>
---
target/sh4/translate.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 878c0bd..fc743da 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -42,6 +42,7 @@ typedef struct DisasContext {
int bstate;
int memidx;
int gbank;
+ int fbank;
uint32_t delayed_pc;
int singlestep_enabled;
uint32_t features;
@@ -365,12 +366,12 @@ static inline void gen_store_fpr64(DisasContext *ctx,
TCGv_i64 t, int reg)
#define REG(x) cpu_gregs[(x) ^ ctx->gbank]
#define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
+#define FREG(x) cpu_fregs[(x) ^ ctx->fbank]
-#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)]
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) FREG(XHACK(x))
+#define XREG(x) FREG(XHACK(x))
/* Assumes lsb of (x) is always 0 */
-#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
+#define DREG(x) ((x) ^ ctx->fbank)
#define CHECK_NOT_DELAY_SLOT \
if (ctx->envflags & DELAY_SLOT_MASK) { \
@@ -2252,6 +2253,7 @@ void gen_intermediate_code(CPUSH4State * env, struct
TranslationBlock *tb)
ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&
(ctx.tbflags & (1 << SR_RB))) * 0x10;
+ ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
--
2.9.4
- Re: [Qemu-devel] [PATCH v2 08/27] linux-user/sh4: Notice gUSA regions during signal delivery, (continued)
- [Qemu-devel] [PATCH v2 09/27] linux-user/sh4: Clean env->flags on signal boundaries, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 10/27] target/sh4: Hoist register bank selection, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 11/27] target/sh4: Unify cpu_fregs into FREG, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 12/27] target/sh4: Pass DisasContext to fpr64 routines, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 13/27] target/sh4: Hoist fp register bank selection,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 14/27] target/sh4: Eliminate unused XREG macro, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 15/27] target/sh4: Merge DREG into fpr64 routines, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 16/27] target/sh4: Load/store Dr as 64-bit quantities, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 17/27] target/sh4: Simplify 64-bit fp reg-reg move, Richard Henderson, 2017/07/06
- [Qemu-devel] [PATCH v2 18/27] target/sh4: Unify code for CHECK_NOT_DELAY_SLOT, Richard Henderson, 2017/07/06