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Re: [Qemu-devel] [PATCH RFC 5/7] s390x/pci: fence off instructions for n


From: Christian Borntraeger
Subject: Re: [Qemu-devel] [PATCH RFC 5/7] s390x/pci: fence off instructions for non-pci
Date: Mon, 10 Jul 2017 14:41:47 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0

On 07/10/2017 01:04 PM, Cornelia Huck wrote:
> On Fri, 7 Jul 2017 15:04:52 +0200
> Cornelia Huck <address@hidden> wrote:
> 
>> On Fri, 7 Jul 2017 14:55:23 +0200
>> Christian Borntraeger <address@hidden> wrote:
>>
>>> On 07/07/2017 02:21 PM, Cornelia Huck wrote:  
>>>> If a guest running on a non-pci build issues a pci instruction,
>>>> throw them an exception.
>>>>
>>>> Signed-off-by: Cornelia Huck <address@hidden>
>>>> ---
>>>>  target/s390x/kvm.c | 24 ++++++++++++++++++++++++
>>>>  1 file changed, 24 insertions(+)
>>>>
>>>> diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
>>>> index a3d00196f4..c5c7c27a21 100644
>>>> --- a/target/s390x/kvm.c
>>>> +++ b/target/s390x/kvm.c
>>>> @@ -1160,6 +1160,9 @@ static int kvm_clp_service_call(S390CPU *cpu, struct 
>>>> kvm_run *run)
>>>>  {
>>>>      uint8_t r2 = (run->s390_sieic.ipb & 0x000f0000) >> 16;
>>>>
>>>> +#ifndef CONFIG_PCI
>>>> +    return -1;
>>>> +#endif    
>>>
>>> Instead of this ifdefing, can you use the cpu model to decide if the 
>>> instruction
>>> should be available? We need to do this anyway for proper handling.
>>>
>>> You can then fence off the PCI bits in the CPU model for
>>> CONFIG_PCI == off.  
>>
>> Sounds like a good idea, I'll give it a try.
>>
>> We'll probably also want to fence off the sclp facility bit via that
>> mechanism.
> 
> Slight problem here... we don't have the relevant facilities defined
> yet, and they are not in the POP (other than "Assigned to IBM internal
> use").
> 
> While I'm pretty sure that the magic number is 69 (judging from the
> Linux code), I think they should be introduced in a patch by someone
> who has access to the documentation including the proper names.

I will try to get some patches out for PCI in the next days that will contain
the PCI related facilities.




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