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Re: [Qemu-devel] [PATCH 11/14] target/mips: Add segmentation control reg
From: |
Yongbok Kim |
Subject: |
Re: [Qemu-devel] [PATCH 11/14] target/mips: Add segmentation control registers |
Date: |
Tue, 18 Jul 2017 23:01:56 +0100 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 |
On 18/07/2017 12:55, James Hogan wrote:
> The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
> CP0_SegCtl2 control the behaviour and required privilege of the legacy
> virtual memory segments.
>
> Add them to the CP0 interface so they can be read and written when
> CP0_Config3.SC=1, and initialise them to describe the standard legacy
> layout so they can be used in future patches regardless of whether they
> are exposed to the guest.
>
> Signed-off-by: James Hogan <address@hidden>
> Cc: Yongbok Kim <address@hidden>
> Cc: Aurelien Jarno <address@hidden>
> ---
> Changes in v2:
> - Use ld_tl and ext32s_tl rather than ld32s_tl to avoid big endian host,
> MIPS64 target issues (Yongbok).
> - Add missing break in DMFC0 CP0_SegCtl2 case.
> ---
> target/mips/cpu.h | 30 ++++++++++++++-
> target/mips/helper.h | 3 +-
> target/mips/machine.c | 7 ++-
> target/mips/op_helper.c | 24 +++++++++++-
> target/mips/translate.c | 88 ++++++++++++++++++++++++++++++++++++++++++-
> 5 files changed, 150 insertions(+), 2 deletions(-)
>
Reviewed-by: Yongbok Kim <address@hidden>
Regards,
Yongbok
- [Qemu-devel] [PATCH 14/14] target/mips: Enable CP0_EBase.WG on MIPS64 CPUs, (continued)
- [Qemu-devel] [PATCH 14/14] target/mips: Enable CP0_EBase.WG on MIPS64 CPUs, James Hogan, 2017/07/18
- [Qemu-devel] [PATCH 8/14] target/mips: Check memory permissions with mem_idx, James Hogan, 2017/07/18
- [Qemu-devel] [PATCH 7/14] target/mips: Decode microMIPS EVA load & store instructions, James Hogan, 2017/07/18
- [Qemu-devel] [PATCH 6/14] target/mips: Decode MIPS32 EVA load & store instructions, James Hogan, 2017/07/18
- [Qemu-devel] [PATCH 13/14] target/mips: Add EVA support to P5600, James Hogan, 2017/07/18
- [Qemu-devel] [PATCH 12/14] target/mips: Implement segmentation control, James Hogan, 2017/07/18
- [Qemu-devel] [PATCH 10/14] target/mips: Add an MMU mode for ERL, James Hogan, 2017/07/18
- [Qemu-devel] [PATCH 11/14] target/mips: Add segmentation control registers, James Hogan, 2017/07/18
- Re: [Qemu-devel] [PATCH 11/14] target/mips: Add segmentation control registers,
Yongbok Kim <=
- [Qemu-devel] [PATCH 5/14] target/mips: Prepare loads/stores for EVA, James Hogan, 2017/07/18
- Re: [Qemu-devel] [PATCH 0/14] target/mips: Add Enhanced Virtual Addressing (EVA) support, no-reply, 2017/07/18