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[Qemu-devel] [PULL 01/14] target/mips: Fix MIPS64 MFC0 UserLocal on BE h
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PULL 01/14] target/mips: Fix MIPS64 MFC0 UserLocal on BE host |
Date: |
Fri, 21 Jul 2017 03:37:02 +0100 |
From: James Hogan <address@hidden>
Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however
CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64
target this reads and sign extends the more significant half of the
64-bit register.
Fix this by using ld_tl to load the whole target_ulong and ext32s_tl to
sign extend it, as done for various other target_ulong COP0 registers.
Fixes: d279279e2b5c ("target-mips: implement UserLocal Register")
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Petar Jovanovic <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1fd18e9..db6e5b5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5144,8 +5144,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
goto cp0_unimplemented;
case 2:
CP0_CHECK(ctx->ulri);
- tcg_gen_ld32s_tl(arg, cpu_env,
- offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
+ tcg_gen_ld_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
+ tcg_gen_ext32s_tl(arg, arg);
rn = "UserLocal";
break;
default:
--
2.7.4
- [Qemu-devel] [PULL 00/14] target-mips queue, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 01/14] target/mips: Fix MIPS64 MFC0 UserLocal on BE host,
Yongbok Kim <=
- [Qemu-devel] [PULL 03/14] target/mips: Weaken TLB flush on UX, SX, KX, ASID changes, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 02/14] target/mips: Fix TLBWI shadow flush for EHINV, XI, RI, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 04/14] target/mips: Add CP0_Ebase.WG (write gate) support, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 07/14] target/mips: Decode microMIPS EVA load & store instructions, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 08/14] target/mips: Check memory permissions with mem_idx, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 06/14] target/mips: Decode MIPS32 EVA load & store instructions, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 13/14] target/mips: Add EVA support to P5600, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 10/14] target/mips: Add an MMU mode for ERL, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 09/14] target/mips: Abstract mmu_idx from hflags, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 05/14] target/mips: Prepare loads/stores for EVA, Yongbok Kim, 2017/07/20