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[Qemu-devel] [PULL 02/14] target/mips: Fix TLBWI shadow flush for EHINV,
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PULL 02/14] target/mips: Fix TLBWI shadow flush for EHINV, XI, RI |
Date: |
Fri, 21 Jul 2017 03:37:03 +0100 |
From: James Hogan <address@hidden>
Writing specific TLB entries with TLBWI flushes shadow TLB entries
unless an existing entry is having its access permissions upgraded. This
is necessary as software would from then on expect the previous mapping
in that entry to no longer be in effect (even if QEMU has quietly
evicted it to the shadow TLB on a TLBWR).
However it won't do this if only EHINV, XI, or RI bits have been set,
even if that results in a reduction of permissions, so add the necessary
checks to invoke the flush when these bits are set.
Fixes: 2fb58b73746e ("target-mips: add RI and XI fields to TLB entry")
Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support")
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Tested-by: Yongbok Kim <address@hidden>
address@hidden:
cosmetic changes]
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/op_helper.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index e5f3ea4..6393eff 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -2029,7 +2029,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env)
int idx;
target_ulong VPN;
uint16_t ASID;
- bool G, V0, D0, V1, D1;
+ bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
tlb = &env->tlb->mmu.r4k.tlb[idx];
@@ -2038,17 +2038,25 @@ void r4k_helper_tlbwi(CPUMIPSState *env)
VPN &= env->SEGMask;
#endif
ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+ EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
V0 = (env->CP0_EntryLo0 & 2) != 0;
D0 = (env->CP0_EntryLo0 & 4) != 0;
+ XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
+ RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
V1 = (env->CP0_EntryLo1 & 2) != 0;
D1 = (env->CP0_EntryLo1 & 4) != 0;
+ XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
+ RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
/* Discard cached TLB entries, unless tlbwi is just upgrading access
permissions on the current entry. */
if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
+ (!tlb->EHINV && EHINV) ||
(tlb->V0 && !V0) || (tlb->D0 && !D0) ||
- (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
+ (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
+ (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
+ (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
}
--
2.7.4
- [Qemu-devel] [PULL 00/14] target-mips queue, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 01/14] target/mips: Fix MIPS64 MFC0 UserLocal on BE host, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 03/14] target/mips: Weaken TLB flush on UX, SX, KX, ASID changes, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 02/14] target/mips: Fix TLBWI shadow flush for EHINV, XI, RI,
Yongbok Kim <=
- [Qemu-devel] [PULL 04/14] target/mips: Add CP0_Ebase.WG (write gate) support, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 07/14] target/mips: Decode microMIPS EVA load & store instructions, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 08/14] target/mips: Check memory permissions with mem_idx, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 06/14] target/mips: Decode MIPS32 EVA load & store instructions, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 13/14] target/mips: Add EVA support to P5600, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 10/14] target/mips: Add an MMU mode for ERL, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 09/14] target/mips: Abstract mmu_idx from hflags, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 05/14] target/mips: Prepare loads/stores for EVA, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 12/14] target/mips: Implement segmentation control, Yongbok Kim, 2017/07/20
- [Qemu-devel] [PULL 14/14] target/mips: Enable CP0_EBase.WG on MIPS64 CPUs, Yongbok Kim, 2017/07/20