[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c:
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same |
Date: |
Fri, 28 Jul 2017 14:00:13 +0100 |
User-agent: |
mu4e 0.9.19; emacs 25.2.50.3 |
Richard Henderson <address@hidden> writes:
> On 07/20/2017 05:04 AM, Alex Bennée wrote:
>> +static softfloat_flags softfloat_mapping_table[] = {
>> + { float_flag_inexact , softfloat_flag_inexact },
>> + { float_flag_underflow, softfloat_flag_underflow },
>> + { float_flag_overflow , softfloat_flag_overflow },
>> + { float_flag_invalid , softfloat_flag_invalid },
>> +};
>> +/* FIXME: 2a has no infinite flag */
>> +
>> +static uint8_t sync_softfloat_flags_from_2a(float_status *flags2a)
>> +{
>> + uint8_t flags = flags2a->float_exception_flags;
>> + int i;
>> + if (flags) {
>> + for (i = 0; i < ARRAY_SIZE(softfloat_mapping_table); i++) {
>> + struct softfloat_flags *map = &softfloat_mapping_table[i];
>> + if (flags & map->float2a_flag) {
>> + softfloat_raiseFlags(map->float3c_flag);
>> + }
>> + }
>> + } else {
>> + softfloat_exceptionFlags = 0;
>> + }
>> +
>> + return softfloat_exceptionFlags;
>> +}
>> +
>
> For conversions like this IMO it's better to make the compiler do the
> work. C.f. target/alpha/fpu_helper.c and CONVERT_BIT.
>
> BTW, I think these TLS variables that softfloat3a are using are going
> to be a real problem. It's one thing to do it temporarily like you
> are here, coordinating between 2a and 3c, but later, when the front
> end is fully converted? That's just nonsense.
>
> Is it going to be worthwhile to significantly hack up the incoming sources?
>
> If so, then we might do something like this: Given a 3c function foo,
>
> T foo_st(T, T, float3a_status *) { ... }
> T foo(T x, T y) { return foo_st(x, y, &tls_status); }
>
> And of course pack all of the relevant state into a struct then
>
> #define softfloat_exceptionFlags tls_status.exceptionflags
>
> etc, instead of having individual tls variables. This feels like
> something that we could push back upstream, assuming that upstream is
> active.
Another option which might be less invasive to the API (although
arguably a bit side-effecty) would be to make:
THREAD_LOCAL uint_fast8_t *softfloat_exceptionFlags;
And add a helper to de-reference softfloat_exceptionFlags when setting
them so that all the:
softfloat_exceptionFlags |= softfloat_flag_inexact;
Become:
softfloat_raiseException(softfloat_flag_inexect);
With something like:
void softfloat_raiseException(uint_fast8_t new)
{
assert(softfloat_exceptionFlags);
*softfloat_exceptionFlags |= new;
}
So new helpers could just do:
uint32_t HELPER(advsimd_foo)(uint32_t a, uint32_t b, void *fpstp)
{
uint_fast8_t *old_fpst = softfloat_exceptionFlags;
softfloat_exceptionFlags = (uint_fast8t *) fpstp;
/* Do stuff */
softfloat_exceptionFlags = old_fpst;
}
Unless there is code that directly fiddles the fpst bits in TCG I think
that should work well enough as any vCPU can only be doing one sort of
float at a time.
Anyway I guess this is all moot until we get an answer as to there being
an active upstream to push stuff back up to. I reached out yesterday
(https://github.com/ucb-bar/berkeley-softfloat-3/issues/5) so we'll see
if we get any feedback. Otherwise I'm minded to stick with 2a and just
implement the half-precision stuff there.
--
Alex Bennée
- [Qemu-devel] [RFC PATCH for 2.11 09/23] arm: introduce ARM_V8_FP16 feature bit, (continued)
- [Qemu-devel] [RFC PATCH for 2.11 09/23] arm: introduce ARM_V8_FP16 feature bit, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 11/23] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 17/23] fpu/softfloat2a: implement propagateFloat16NaN, Alex Bennée, 2017/07/20
- [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/20
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Richard Henderson, 2017/07/20
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/21
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Aurelien Jarno, 2017/07/21
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/07/21
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Peter Maydell, 2017/07/21
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Aurelien Jarno, 2017/07/21
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same,
Alex Bennée <=
- Re: [Qemu-devel] [RFC PATCH for 2.11 12/23] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Richard Henderson, 2017/07/28
[Qemu-devel] [RFC PATCH for 2.11 04/23] softfloat3c: fixup include paths, Alex Bennée, 2017/07/20
[Qemu-devel] [RFC PATCH for 2.11 15/23] target/arm/translate-a64.c: AdvSIMD scalar 2 register misc decode, Alex Bennée, 2017/07/20
[Qemu-devel] [RFC PATCH for 2.11 22/23] fpu/softfloat2a: improve comments on ARM NaN propagation, Alex Bennée, 2017/07/20
[Qemu-devel] [RFC PATCH for 2.11 23/23] target/arm: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2017/07/20
[Qemu-devel] [RFC PATCH for 2.11 18/23] fpu/softfloat2a: implement float16_squash_input_denormal, Alex Bennée, 2017/07/20
[Qemu-devel] [RFC PATCH for 2.11 14/23] target/arm/translate-a64.c: add ARMv8.2 fadd scalar half-precision, Alex Bennée, 2017/07/20