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Re: [Qemu-devel] [PATCH v2 for-2.10 3/3] target/arm: Require alignment f
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 for-2.10 3/3] target/arm: Require alignment for load exclusive |
Date: |
Tue, 15 Aug 2017 09:32:29 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 |
On 08/15/2017 08:56 AM, Philippe Mathieu-Daudé wrote:
>> @@ -1885,7 +1886,7 @@ static void gen_load_exclusive(DisasContext *s, int rt,
>> int rt2,
>> tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high);
>> }
>> } else {
>> - memop |= size;
>> + memop |= size | MO_ALIGN;
>
> MO_ALIGN_8 here too?
>
>> tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
>> tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
Peter already pointed out that MO_ALIGN_N should be reserved for those cases
where an explicit size really needed. You should note that using MO_ALIGN_8
would be actively wrong here -- it would incorrectly require 8 byte alignment
for the single byte access of LDXRB.
r~
Re: [Qemu-devel] [PATCH v2 for-2.10 0/3] Fixup logic for exclusive pair, Peter Maydell, 2017/08/15