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[Qemu-devel] [PULL 12/36] target/arm: Don't calculate lr in arm_v7m_cpu_
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/36] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed |
Date: |
Mon, 4 Sep 2017 13:25:43 +0100 |
Move the code in arm_v7m_cpu_do_interrupt() that calculates the
magic LR value down to when we're actually going to use it.
Having the calculation and use so far apart makes the code
a little harder to understand than it needs to be.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9410856..267a170 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6306,13 +6306,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
arm_log_exception(cs->exception_index);
- lr = 0xfffffff1;
- if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
- lr |= 4;
- }
- if (env->v7m.exception == 0)
- lr |= 8;
-
/* For exceptions we just mark as pending on the NVIC, and let that
handle it. */
switch (cs->exception_index) {
@@ -6403,6 +6396,14 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */
}
+ lr = 0xfffffff1;
+ if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {
+ lr |= 4;
+ }
+ if (env->v7m.exception == 0) {
+ lr |= 8;
+ }
+
v7m_push_stack(cpu);
v7m_exception_taken(cpu, lr);
qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception);
--
2.7.4
- [Qemu-devel] [PULL 04/36] target/arm: Tighten up Thumb decode where new v8M insns will be, (continued)
- [Qemu-devel] [PULL 04/36] target/arm: Tighten up Thumb decode where new v8M insns will be, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 03/36] target/arm: Consolidate PMSA handling in get_phys_addr(), Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 06/36] target/arm: Remove incorrect comment about MPU_CTRL, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 07/36] target/arm: Fix outdated comment about exception exit, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 01/36] target/arm: Use MMUAccessType enum rather than int, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 02/36] target/arm: Don't trap WFI/WFE for M profile, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 08/36] target/arm: Define and use XPSR bit masks, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 09/36] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 10/36] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 11/36] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 12/36] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed,
Peter Maydell <=
- [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode(), Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 18/36] hw/arm: use defined type name instead of hard-coded string, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 15/36] nvic: Implement "user accesses BusFault" SCS region behaviour, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 14/36] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 16/36] loader: Handle ELF files with overlapping zero-initialized data, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 19/36] hw/arm/virt: add pmu interrupt state, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 22/36] target/arm/kvm: pmu: improve error handling, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 17/36] loader: Ignore zero-sized ELF segments, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 21/36] hw/arm/virt: allow pmu instantiation with userspace irqchip, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 24/36] aspeed_soc: Propagate silicon-rev to watchdog, Peter Maydell, 2017/09/04