[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 19/36] hw/arm/virt: add pmu interrupt state
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/36] hw/arm/virt: add pmu interrupt state |
Date: |
Mon, 4 Sep 2017 13:25:50 +0100 |
From: Andrew Jones <address@hidden>
Mimicking gicv3-maintenance-interrupt, add the PMU's interrupt to
CPU state.
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 2 ++
hw/arm/virt.c | 3 +++
target/arm/cpu.c | 2 ++
3 files changed, 7 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index eabef00..92771d3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -585,6 +585,8 @@ struct ARMCPU {
qemu_irq gt_timer_outputs[NUM_GTIMERS];
/* GPIO output for GICv3 maintenance interrupt signal */
qemu_irq gicv3_maintenance_interrupt;
+ /* GPIO output for the PMU interrupt */
+ qemu_irq pmu_interrupt;
/* MemoryRegion to use for secure physical accesses */
MemoryRegion *secure_memory;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6b7a0fe..a06ec13 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -610,6 +610,9 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
qdev_get_gpio_in(gicdev, ppibase
+ ARCH_GICV3_MAINT_IRQ));
+ qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
+ qdev_get_gpio_in(gicdev, ppibase
+ + VIRTUAL_PMU_IRQ));
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev,
ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b241a63..41ae6ba 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -508,6 +508,8 @@ static void arm_cpu_initfn(Object *obj)
qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
"gicv3-maintenance-interrupt", 1);
+ qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
+ "pmu-interrupt", 1);
#endif
/* DTB consumers generally don't in fact care what the 'compatible'
--
2.7.4
- [Qemu-devel] [PULL 08/36] target/arm: Define and use XPSR bit masks, (continued)
- [Qemu-devel] [PULL 08/36] target/arm: Define and use XPSR bit masks, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 09/36] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 10/36] target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 11/36] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 12/36] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode(), Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 18/36] hw/arm: use defined type name instead of hard-coded string, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 15/36] nvic: Implement "user accesses BusFault" SCS region behaviour, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 14/36] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 16/36] loader: Handle ELF files with overlapping zero-initialized data, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 19/36] hw/arm/virt: add pmu interrupt state,
Peter Maydell <=
- [Qemu-devel] [PULL 22/36] target/arm/kvm: pmu: improve error handling, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 17/36] loader: Ignore zero-sized ELF segments, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 21/36] hw/arm/virt: allow pmu instantiation with userspace irqchip, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 24/36] aspeed_soc: Propagate silicon-rev to watchdog, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 25/36] memory.h: Move MemTxResult type to memattrs.h, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 20/36] target/arm/kvm: pmu: split init and set-irq stages, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 23/36] watchdog: wdt_aspeed: Add support for the reset width register, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 26/36] cpu: Define new cpu_transaction_failed() hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 32/36] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/04
- [Qemu-devel] [PULL 34/36] hw/arm/digic: Mark device with user_creatable = false, Peter Maydell, 2017/09/04