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[Qemu-devel] [PULL 03/14] tcg: Implement implicit ordering semantics
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 03/14] tcg: Implement implicit ordering semantics |
Date: |
Wed, 6 Sep 2017 07:49:29 -0700 |
From: Pranith Kumar <address@hidden>
Currently, we cannot use mttcg for running strong memory model guests
on weak memory model hosts due to missing ordering semantics.
We implicitly generate fence instructions for stronger guests if an
ordering mismatch is detected. We generate fences only for the orders
for which fence instructions are necessary, for example a fence is not
necessary between a store and a subsequent load on x86 since its
absence in the guest binary tells that ordering need not be
ensured. Also note that if we find multiple subsequent fence
instructions in the generated IR, we combine them in the TCG
optimization pass.
This patch allows us to boot an x86 guest on ARM64 hosts using mttcg.
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg-op.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 87f673ef49..688d91755b 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -28,6 +28,7 @@
#include "exec/exec-all.h"
#include "tcg.h"
#include "tcg-op.h"
+#include "tcg-mo.h"
#include "trace-tcg.h"
#include "trace/mem.h"
@@ -2662,8 +2663,20 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val,
TCGv addr,
#endif
}
+static void tcg_gen_req_mo(TCGBar type)
+{
+#ifdef TCG_GUEST_DEFAULT_MO
+ type &= TCG_GUEST_DEFAULT_MO;
+#endif
+ type &= ~TCG_TARGET_DEFAULT_MO;
+ if (type) {
+ tcg_gen_mb(type | TCG_BAR_SC);
+ }
+}
+
void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
addr, trace_mem_get_info(memop, 0));
@@ -2672,6 +2685,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg
idx, TCGMemOp memop)
void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
+ tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
addr, trace_mem_get_info(memop, 1));
@@ -2680,6 +2694,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg
idx, TCGMemOp memop)
void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
+ tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
if (memop & MO_SIGN) {
@@ -2698,6 +2713,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg
idx, TCGMemOp memop)
void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
+ tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
return;
--
2.13.5
- [Qemu-devel] [PULL 00/14] TCG misc queued patches, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 02/14] tcg: Add tcg target default memory ordering, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 03/14] tcg: Implement implicit ordering semantics,
Richard Henderson <=
- [Qemu-devel] [PULL 04/14] disas/i386: Fix disassembly of two-byte vex prefixes, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 05/14] disas/i386: Add disassembly of vex.0f38.f5, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 08/14] tcg/s390: Merge cmpi facilities check to tcg_target_op_def, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 07/14] tcg/s390: Fully convert tcg_target_op_def, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 09/14] tcg/s390: Merge muli facilities check to tcg_target_op_def, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 06/14] disas/i386: Add disassembly of rorx, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 11/14] tcg/s390: Merge ori+xori facilities check to tcg_target_op_def, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 13/14] tcg/s390: Use load-on-condition-2 facility, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 10/14] tcg/s390: Merge add2i facilities check to tcg_target_op_def, Richard Henderson, 2017/09/06
- [Qemu-devel] [PULL 12/14] tcg/s390: Use distinct-operands facility, Richard Henderson, 2017/09/06