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[Qemu-devel] [PULL 04/31] xlnx_zynqmp: Convert to DEFINE_PROP_LINK
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/31] xlnx_zynqmp: Convert to DEFINE_PROP_LINK |
Date: |
Thu, 7 Sep 2017 14:27:57 +0100 |
From: Fam Zheng <address@hidden>
Signed-off-by: Fam Zheng <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/xlnx-zynqmp.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 9eceadb..22c2a33 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -140,11 +140,6 @@ static void xlnx_zynqmp_init(Object *obj)
&error_abort);
}
- object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
- (Object **)&s->ddr_ram,
- qdev_prop_allow_set_link_before_realize,
- OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
-
object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
@@ -433,6 +428,8 @@ static Property xlnx_zynqmp_props[] = {
DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
+ DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
DEFINE_PROP_END_OF_LIST()
};
--
2.7.4
- [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 15/31] target/arm: Make FAULTMASK register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 14/31] target/arm: Make PRIMASK register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 01/31] armv7m: Convert bitband.source-memory to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 18/31] target/arm: Make VTOR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 13/31] target/arm: Make BASEPRI register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 12/31] target/arm: Add MMU indexes for secure v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 11/31] target/arm: Register second AddressSpace for secure v8M CPUs, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 07/31] hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = false, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 10/31] target/arm: Add state field, feature bit and migration for v8M secure state, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 04/31] xlnx_zynqmp: Convert to DEFINE_PROP_LINK,
Peter Maydell <=
- [Qemu-devel] [PULL 09/31] target/arm: Implement new PMSAv8 behaviour, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 20/31] target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 17/31] nvic: Add NS alias SCS region, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 03/31] gicv3: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 21/31] target/arm: Make MPU_RNR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 08/31] target/arm: Implement ARMv8M's PMSAv8 registers, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 19/31] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 06/31] xilinx_axidma: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 25/31] target/arm: Make CFSR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 23/31] target/arm: Make CCR register banked for v8M, Peter Maydell, 2017/09/07