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Re: [Qemu-devel] [RFC PATCH 16/26] ppc/xive: notify CPU when interrupt p
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From: |
Cédric Le Goater |
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Subject: |
Re: [Qemu-devel] [RFC PATCH 16/26] ppc/xive: notify CPU when interrupt priority is more privileged |
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Date: |
Sat, 9 Sep 2017 10:24:58 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 09/09/2017 09:39 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2017-07-05 at 19:13 +0200, Cédric Le Goater wrote:
>> Signed-off-by: Cédric Le Goater <address@hidden>
>> ---
>> hw/intc/xive.c | 21 +++++++++++++++++++++
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
>> index c3c1e9c9db2d..cda1fa18e44d 100644
>> --- a/hw/intc/xive.c
>> +++ b/hw/intc/xive.c
>> @@ -53,6 +53,21 @@ static uint64_t xive_icp_accept(XiveICPState *xicp)
>> return (nsr << 8) | xicp->tima_os[TM_CPPR];
>> }
>>
>> +static uint8_t ipb_to_pipr(uint8_t ibp)
>> +{
>> + return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
>> +}
>
> The PIPR needs to be updated also on accept etc... anything that change
> IPBs or CPPR really.
but not for the SET_OS_PENDING special write I suppose.
C.