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From: | Philippe Mathieu-Daudé |
Subject: | Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers |
Date: | Tue, 12 Sep 2017 15:50:11 -0300 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
Hi Richard, On 09/12/2017 01:25 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson <address@hidden> --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26fd3..419f008277 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -486,7 +486,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; + float64 regs[64] __attribute__((aligned(16)));
I understand this should be aligned to the biggest vector register the host support, i.e. for AVX-512 this would be QEMU_ALIGNED(64), is it correct?
I'd rather use a #define such HOST_VECTOR_LENGTH_BITS_MAX and QEMU_ALIGNED(HOST_VECTOR_LENGTH_BITS_MAX / BITS_PER_BYTE) or directly QEMU_ALIGNED(HOST_VECTOR_LENGTH_MAX), using the define makes it self-explanatory. Or shorter:
float64 regs[64] QEMU_ALIGNED(HOST_VECTOR_SIZE); What do you think? Regards, Phil.
uint32_t xregs[16];/* We store these fpcsr fields separately for convenience. */
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