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[Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M |
Date: |
Fri, 22 Sep 2017 15:59:55 +0100 |
In the v8M architecture, return from an exception to a PC which
has bit 0 set is not UNPREDICTABLE; it is defined that bit 0
is discarded [R_HRJH]. Restrict our complaint about this to v7M.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 979129e..59a07d2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6421,16 +6421,22 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
env->regs[12] = ldl_phys(cs->as, frameptr + 0x10);
env->regs[14] = ldl_phys(cs->as, frameptr + 0x14);
env->regs[15] = ldl_phys(cs->as, frameptr + 0x18);
- if (env->regs[15] & 1) {
+
+ /* Returning from an exception with a PC with bit 0 set is defined
+ * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
+ * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
+ * the lsbit, and there are several RTOSes out there which incorrectly
+ * assume the r15 in the stack frame should be a Thumb-style "lsbit
+ * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
+ * complain about the badly behaved guest.
+ */
+ if ((env->regs[15] & 1) && !arm_feature(env, ARM_FEATURE_V8)) {
qemu_log_mask(LOG_GUEST_ERROR,
"M profile return from interrupt with misaligned "
- "PC is UNPREDICTABLE\n");
- /* Actual hardware seems to ignore the lsbit, and there are several
- * RTOSes out there which incorrectly assume the r15 in the stack
- * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
- */
- env->regs[15] &= ~1U;
+ "PC is UNPREDICTABLE on v7M\n");
}
+ env->regs[15] &= ~1U;
+
xpsr = ldl_phys(cs->as, frameptr + 0x1c);
if (arm_feature(env, ARM_FEATURE_V8)) {
--
2.7.4
- [Qemu-devel] [PATCH 00/20] ARM v8M: exception entry, exit and security, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 04/20] target/arm: Restore security state on exception return, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register on exception return, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M,
Peter Maydell <=
- [Qemu-devel] [PATCH 10/20] target/arm: Update excret sanity checks for v8M, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution Unit registers, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS, Peter Maydell, 2017/09/22
- [Qemu-devel] [PATCH 16/20] target/arm: Factor out "get mmuidx for specified security state", Peter Maydell, 2017/09/22