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[Qemu-devel] [PATCH 5/9] target-arm: Don't check for "Thumb2 or M profil
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 5/9] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 |
Date: |
Mon, 9 Oct 2017 14:48:35 +0100 |
The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).
This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 58d706c..f5ca87f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9722,8 +9722,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
int conds;
int logic_cc;
- if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
- || arm_dc_feature(s, ARM_FEATURE_M))) {
+ if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
/* Thumb-1 cores may need to treat bl and blx as a pair of
16-bit instructions to get correct prefetch abort behavior. */
insn = insn_hw1;
--
2.7.4
- [Qemu-devel] [PATCH 0/9] v8M: BLXNS, SG, secure function return, Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 8/9] target/arm: Support some Thumb insns being always unconditional, Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 7/9] target-arm: Simplify insn_crosses_page(), Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 6/9] target/arm: Pull Thumb insn word loads up to top level, Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 3/9] target/arm: Implement BLXNS, Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 5/9] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1,
Peter Maydell <=
- [Qemu-devel] [PATCH 2/9] target/arm: Implement SG instruction, Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 9/9] target/arm: Implement SG instruction corner cases, Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 1/9] target/arm: Add M profile secure MMU index values to get_a32_user_mem_index(), Peter Maydell, 2017/10/09
- [Qemu-devel] [PATCH 4/9] target/arm: Implement secure function return, Peter Maydell, 2017/10/09